Lines Matching refs:Tb
2286 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2294 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2295 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2296 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2299 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2300 ushll(Vd, Ta, Vn, Tb, shift);
2329 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2331 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2332 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2334 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2337 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2338 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2339 pmull(Vd, Ta, Vn, Vm, Tb);
2342 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2344 int size_b = (int)Tb >> 1;
2347 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);