dev/pci/ichwdt.c

77 ichwdt_unlock_write(struct ichwdt_softc *sc, int reg, u_int32_t val)
80 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, ICH_WDT_RELOAD, 0x80);
81 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, ICH_WDT_RELOAD, 0x86);
84 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
97 	struct ichwdt_softc *sc = (struct ichwdt_softc *)self;
101 	sc->sc_pc = pa->pa_pc;
102 	sc->sc_tag = pa->pa_tag;
105 	sc->sc_iot = pa->pa_iot;
107 	    &sc->sc_iot, &sc->sc_ioh, NULL, NULL, 0)) {
113 	reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ICH_WDT_CONF);
117 	sc->sc_divisor = (reg & ICH_WDT_CONF_PRE ? 32 : 32768);
123 	pci_conf_write(sc->sc_pc, sc->sc_tag, ICH_WDT_CONF, reg);
126 	reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ICH_WDT_RELOAD);
131 		ichwdt_unlock_write(sc, ICH_WDT_RELOAD,
136 	pci_conf_write(sc->sc_pc, sc->sc_tag, ICH_WDT_LOCK, 0);
137 	sc->sc_period = 0;
142 	wdog_register(ichwdt_cb, sc);
160 	struct ichwdt_softc *sc = arg;
164 		if (sc->sc_period != 0) {
166 			ichwdt_unlock_write(sc, ICH_WDT_RELOAD,
168 			pci_conf_write(sc->sc_pc, sc->sc_tag, ICH_WDT_LOCK, 0);
170 			    sc->sc_dev.dv_xname,
171 			    pci_conf_read(sc->sc_pc, sc->sc_tag,
179 		if (sc->sc_period != period) {
181 			nticks = (period * 33000000) / sc->sc_divisor;
182 			ichwdt_unlock_write(sc, ICH_WDT_PRE1, nticks);
183 			ichwdt_unlock_write(sc, ICH_WDT_PRE2, 2);
185 			    sc->sc_dev.dv_xname, period, nticks));
187 		if (sc->sc_period == 0) {
189 			pci_conf_write(sc->sc_pc, sc->sc_tag, ICH_WDT_LOCK,
192 			    sc->sc_dev.dv_xname,
193 			    pci_conf_read(sc->sc_pc, sc->sc_tag,
197 			ichwdt_unlock_write(sc, ICH_WDT_RELOAD,
199 			DPRINTF(("%s: reloaded\n", sc->sc_dev.dv_xname));
202 	sc->sc_period = period;