drm/radeon/si_dpm.c

1734 					 struct rv7xx_pl *pl,
4273 						struct rv7xx_pl *pl,
4281 		(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4284 					    pl->sclk,
4285 					    pl->mclk);
4618 	ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4647 	ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4740 	if (ulv->supported && ulv->pl.vddc) {
4959 					 struct rv7xx_pl *pl,
4974 		level->gen2PCIE = (u8)pl->pcie_gen;
4976 	ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4983 	    (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4994 		if (pl->mclk > pi->mclk_edc_enable_threshold)
4997 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5000 		level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5003 			if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5013 								pl->mclk);
5019 				     pl->sclk,
5020 				     pl->mclk,
5028 					pl->vddc, &level->vddc);
5044 						pl->vddci, &level->vddci);
5052 						       pl->vddc,
5053 						       pl->sclk,
5054 						       pl->mclk,
5062 	ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5136 	if (state->performance_levels[0].mclk != ulv->pl.mclk)
5144 			if (ulv->pl.vddc <
5280 	if (ulv->supported && ulv->pl.vddc) {
5598 						 struct rv7xx_pl *pl,
5605 		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5653 	if (ulv->supported && ulv->pl.vddc != 0)
5654 		si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
6721 	struct rv7xx_pl *pl = &ps->performance_levels[index];
6726 	pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6727 	pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6728 	pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6729 	pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6731 	pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6732 	pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6733 	pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6734 	pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6740 	ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6743 		pl->vddc = leakage_voltage;
6746 		pi->acpi_vddc = pl->vddc;
6747 		eg_pi->acpi_vddci = pl->vddci;
6748 		si_pi->acpi_pcie_gen = pl->pcie_gen;
6755 		si_pi->ulv.pl = *pl;
6762 	if (pi->min_vddc_in_table > pl->vddc)
6763 		pi->min_vddc_in_table = pl->vddc;
6765 	if (pi->max_vddc_in_table < pl->vddc)
6766 		pi->max_vddc_in_table = pl->vddc;
6772 		pl->mclk = rdev->clock.default_mclk;
6773 		pl->sclk = rdev->clock.default_sclk;
6774 		pl->vddc = vddc;
6775 		pl->vddci = vddci;
6781 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6782 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6783 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6784 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7078 	struct rv7xx_pl *pl;
7086 		pl = &ps->performance_levels[current_index];
7089 			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7098 	struct rv7xx_pl *pl;
7106 		pl = &ps->performance_levels[current_index];
7107 		return pl->sclk;
7116 	struct rv7xx_pl *pl;
7124 		pl = &ps->performance_levels[current_index];
7125 		return pl->mclk;