Lines Matching defs:idx_value
1636 u32 idx_value;
1641 idx_value = radeon_get_ib_value(p, idx);
1674 (idx_value & 0xfffffff0) +
1715 idx_value +
1757 if (idx_value & 0x10) {
1772 } else if (idx_value & 0x100) {
1909 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1925 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1945 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
2025 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2036 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2046 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2056 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2070 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2089 if (idx_value > 3) {
2102 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2108 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2110 offset, track->vgt_strmout_bo_offset[idx_value]);
2138 if (idx_value & 0x1) {
2157 if (((idx_value >> 1) & 0x3) == 2) {
2210 if (idx_value & 0x1) {
2234 if (idx_value & 0x2) {
2382 u32 idx, idx_value;
2437 idx_value = radeon_get_ib_value(p, idx + 2);
2439 if (idx_value & (1 << 31)) {