drm/radeon/evergreen_cs.c

1221 		track->db_z_read_bo = reloc->robj;
1233 		track->db_z_write_bo = reloc->robj;
1245 		track->db_s_read_bo = reloc->robj;
1257 		track->db_s_write_bo = reloc->robj;
1281 		track->vgt_strmout_bo[tmp] = reloc->robj;
1505 		track->cb_color_fmask_bo[tmp] = reloc->robj;
1522 		track->cb_color_cmask_bo[tmp] = reloc->robj;
1563 		track->cb_color_bo[tmp] = reloc->robj;
1579 		track->cb_color_bo[tmp] = reloc->robj;
1591 		track->htile_bo = reloc->robj;
2022 		track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj);
2159 				if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2161 						 tmp + size, radeon_bo_size(reloc->robj));
2197 				if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2199 						 tmp + size, radeon_bo_size(reloc->robj));
2376 				texture = reloc->robj;
2397 					mipmap = reloc->robj;
2417 				if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2420 					ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2499 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2501 					  offset + 4, radeon_bo_size(reloc->robj));
2518 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2520 					  offset + 4, radeon_bo_size(reloc->robj));
2547 		if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2549 				  offset + 8, radeon_bo_size(reloc->robj));
2572 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2574 					  offset + 4, radeon_bo_size(reloc->robj));
2599 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2601 					  offset + 4, radeon_bo_size(reloc->robj));
2847 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2849 					 dst_offset, radeon_bo_size(dst_reloc->robj));
2872 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2874 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2877 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2879 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2912 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2914 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2917 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2919 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2931 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
2933 							src_offset + count, radeon_bo_size(src_reloc->robj));
2936 				if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
2938 							dst_offset + count, radeon_bo_size(dst_reloc->robj));
2975 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2977 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2980 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2982 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2985 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2987 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3015 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3017 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3020 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3022 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3025 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3027 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3077 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3079 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3082 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3084 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3087 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3089 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3123 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3125 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3128 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3130 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3164 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3166 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3169 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3171 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3174 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3176 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3198 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3200 					 dst_offset, radeon_bo_size(dst_reloc->robj));