drm/radeon/atombios_dp.c

553 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
556 	atombios_dig_transmitter_setup(dp_info->encoder,
558 				       0, dp_info->train_set[0]); /* sets all lanes at once */
561 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
562 			  dp_info->train_set, dp_info->dp_lane_count);
565 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
570 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
582 		atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
592 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
593 					  dp_info->dp_clock, dp_info->enc_id, rtp);
597 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
600 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
602 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
607 	radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
610 	if (dp_info->dpcd[3] & 0x1)
611 		drm_dp_dpcd_writeb(dp_info->aux,
614 		drm_dp_dpcd_writeb(dp_info->aux,
618 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
621 	tmp = dp_info->dp_lane_count;
622 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
624 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
627 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
628 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
631 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
632 		atombios_dig_encoder_setup(dp_info->encoder,
635 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
636 					  dp_info->dp_clock, dp_info->enc_id, 0);
639 	drm_dp_dpcd_writeb(dp_info->aux,
646 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
651 	drm_dp_dpcd_writeb(dp_info->aux,
656 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
657 		atombios_dig_encoder_setup(dp_info->encoder,
660 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
661 					  dp_info->dp_clock, dp_info->enc_id, 0);
666 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
672 	radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
673 	memset(dp_info->train_set, 0, 4);
674 	radeon_dp_update_vs_emph(dp_info);
680 	dp_info->tries = 0;
683 		drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
685 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
686 						 dp_info->link_status) <= 0) {
691 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
696 		for (i = 0; i < dp_info->dp_lane_count; i++) {
697 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
700 		if (i == dp_info->dp_lane_count) {
705 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
706 			++dp_info->tries;
707 			if (dp_info->tries == 5) {
712 			dp_info->tries = 0;
714 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
717 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
719 		radeon_dp_update_vs_emph(dp_info);
726 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
727 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
733 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
737 	if (dp_info->tp3_supported)
738 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
740 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
743 	dp_info->tries = 0;
746 		drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
748 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
749 						 dp_info->link_status) <= 0) {
754 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
760 		if (dp_info->tries > 5) {
766 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
768 		radeon_dp_update_vs_emph(dp_info);
769 		dp_info->tries++;
777 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
778 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
793 	struct radeon_dp_link_train_info dp_info;
814 	dp_info.use_dpencoder = true;
818 			dp_info.use_dpencoder = false;
821 	dp_info.enc_id = 0;
823 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
825 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
827 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
829 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
834 			dp_info.tp3_supported = true;
836 			dp_info.tp3_supported = false;
838 		dp_info.tp3_supported = false;
841 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
842 	dp_info.rdev = rdev;
843 	dp_info.encoder = encoder;
844 	dp_info.connector = connector;
845 	dp_info.dp_lane_count = dig_connector->dp_lane_count;
846 	dp_info.dp_clock = dig_connector->dp_clock;
847 	dp_info.aux = &radeon_connector->ddc_bus->aux;
849 	if (radeon_dp_link_train_init(&dp_info))
851 	if (radeon_dp_link_train_cr(&dp_info))
853 	if (radeon_dp_link_train_ce(&dp_info))
856 	if (radeon_dp_link_train_finish(&dp_info))