i915/soc/intel_gmch.c

26 	i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
27 	if (!i915->gmch.pdev) {
33 					i915->gmch.pdev);
41 	if (i915->gmch.pdev != NULL)
44 	i915->gmch.pdev = malloc(sizeof(*i915->gmch.pdev),
46 	i915->gmch.pdev->pc = dev->pdev->pc;
47 	i915->gmch.pdev->tag = pci_make_tag(dev->pdev->pc, 0, 0, 0);
50 					i915->gmch.pdev);
64 		pci_read_config_dword(i915->gmch.pdev, reg + 4, &temp_hi);
65 	pci_read_config_dword(i915->gmch.pdev, reg, &temp_lo);
77 	i915->gmch.mch_res.name = "i915 MCHBAR";
78 	i915->gmch.mch_res.flags = IORESOURCE_MEM;
79 	ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
80 				     &i915->gmch.mch_res,
84 				     i915->gmch.pdev);
87 		i915->gmch.mch_res.start = 0;
92 	    MCHBAR_SIZE, MCHBAR_SIZE, 0, 0, 0, &i915->gmch.mch_res.start)) {
98 		pci_write_config_dword(i915->gmch.pdev, reg + 4,
99 				       upper_32_bits(i915->gmch.mch_res.start));
101 	pci_write_config_dword(i915->gmch.pdev, reg,
102 			       lower_32_bits(i915->gmch.mch_res.start));
116 	i915->gmch.mchbar_need_disable = false;
119 		pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
122 		pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
133 	i915->gmch.mchbar_need_disable = true;
137 		pci_write_config_dword(i915->gmch.pdev, DEVEN,
140 		pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
141 		pci_write_config_dword(i915->gmch.pdev, mchbar_reg, temp | 1);
149 	if (i915->gmch.mchbar_need_disable) {
153 			pci_read_config_dword(i915->gmch.pdev, DEVEN,
156 			pci_write_config_dword(i915->gmch.pdev, DEVEN,
161 			pci_read_config_dword(i915->gmch.pdev, mchbar_reg,
164 			pci_write_config_dword(i915->gmch.pdev, mchbar_reg,
169 	if (i915->gmch.mch_res.start)
171 		release_resource(&i915->gmch.mch_res);
173 		extent_free(i915->memex, i915->gmch.mch_res.start,
183 	if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
196 	if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {