i915/gt/intel_rc6.c

70 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
71 		intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
73 		intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
74 		intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
76 			intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
78 		intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
80 		intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
82 		intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
103 	intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
104 	intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
143 	intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
154 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
155 		intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
161 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
163 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
166 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
167 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
169 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
171 	intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
173 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
196 	intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
197 	intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
200 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
212 		intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
223 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
224 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
225 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
227 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
228 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
229 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
247 	intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
248 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
249 	intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
250 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
251 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
254 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
256 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
257 	intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
258 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
259 	intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
260 	intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
374 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
375 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
376 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
379 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
380 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
383 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
386 	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
401 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
402 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
403 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
406 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
408 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
411 	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
577 		intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
578 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
579 	intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
690 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
710 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
718 	intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
741 		intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
772 	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
778 		intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
782 		intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,