i915/gt/gen2_engine_cs.c

19 	u32 cmd, *cs;
25 	cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);
26 	if (IS_ERR(cs))
27 		return PTR_ERR(cs);
29 	*cs++ = cmd;
31 		*cs++ = MI_STORE_DWORD_INDEX;
32 		*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
33 		*cs++ = 0;
34 		*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
36 	*cs++ = cmd;
38 	intel_ring_advance(rq, cs);
45 	u32 cmd, *cs;
87 	cs = intel_ring_begin(rq, i);
88 	if (IS_ERR(cs))
89 		return PTR_ERR(cs);
91 	*cs++ = cmd;
104 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
105 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
108 		*cs++ = 0;
109 		*cs++ = 0;
112 			*cs++ = MI_FLUSH;
114 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
115 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
118 		*cs++ = 0;
119 		*cs++ = 0;
122 	*cs++ = cmd;
124 	intel_ring_advance(rq, cs);
131 	u32 *cs;
133 	cs = intel_ring_begin(rq, 2);
134 	if (IS_ERR(cs))
135 		return PTR_ERR(cs);
137 	*cs++ = MI_FLUSH;
138 	*cs++ = MI_NOOP;
139 	intel_ring_advance(rq, cs);
144 static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
150 	*cs++ = MI_FLUSH;
153 		*cs++ = MI_STORE_DWORD_INDEX;
154 		*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);
155 		*cs++ = rq->fence.seqno;
159 		*cs++ = MI_STORE_DWORD_INDEX;
160 		*cs++ = I915_GEM_HWS_SEQNO_ADDR;
161 		*cs++ = rq->fence.seqno;
164 	*cs++ = MI_USER_INTERRUPT;
166 	rq->tail = intel_ring_offset(rq, cs);
169 	return cs;
172 u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
174 	return __gen2_emit_breadcrumb(rq, cs, 16, 8);
177 u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
179 	return __gen2_emit_breadcrumb(rq, cs, 8, 8);
190 	u32 *cs, cs_offset =
196 	cs = intel_ring_begin(rq, 6);
197 	if (IS_ERR(cs))
198 		return PTR_ERR(cs);
201 	*cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
202 	*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
203 	*cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
204 	*cs++ = cs_offset;
205 	*cs++ = 0xdeadbeef;
206 	*cs++ = MI_NOOP;
207 	intel_ring_advance(rq, cs);
213 		cs = intel_ring_begin(rq, 6 + 2);
214 		if (IS_ERR(cs))
215 			return PTR_ERR(cs);
222 		*cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
223 		*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
224 		*cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
225 		*cs++ = cs_offset;
226 		*cs++ = 4096;
227 		*cs++ = offset;
229 		*cs++ = MI_FLUSH;
230 		*cs++ = MI_NOOP;
231 		intel_ring_advance(rq, cs);
240 	cs = intel_ring_begin(rq, 2);
241 	if (IS_ERR(cs))
242 		return PTR_ERR(cs);
244 	*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
245 	*cs++ = offset;
246 	intel_ring_advance(rq, cs);
255 	u32 *cs;
260 	cs = intel_ring_begin(rq, 2);
261 	if (IS_ERR(cs))
262 		return PTR_ERR(cs);
264 	*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
265 	*cs++ = offset;
266 	intel_ring_advance(rq, cs);
276 	u32 *cs;
282 	cs = intel_ring_begin(rq, 2);
283 	if (IS_ERR(cs))
284 		return PTR_ERR(cs);
286 	*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security;
287 	*cs++ = offset;
288 	intel_ring_advance(rq, cs);