i915/display/intel_gmbus.c

80 /* Map gmbus pin pairs to names and registers. */
488 	add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
499 	remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
519 	add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
525 	remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
683  * The gmbus controller can combine a 1 or 2 byte write with another read/write
768 	/* Generate a STOP condition on the bus. Note that gmbus can't generata
770 	 * unconditionally generate the STOP condition with an additional gmbus
798 	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
908 	mutex_lock(&i915->display.gmbus.mutex);
917 	mutex_unlock(&i915->display.gmbus.mutex);
943 	mutex_lock(&i915->display.gmbus.mutex);
952 	return mutex_trylock(&i915->display.gmbus.mutex);
961 	mutex_unlock(&i915->display.gmbus.mutex);
983 		i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
989 		i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
991 	rw_init(&i915->display.gmbus.mutex, "gmbus");
992 	init_waitqueue_head(&i915->display.gmbus.wait_queue);
994 	for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
1014 			 "i915 gmbus %s", gmbus_pin->name);
1033 		/* gmbus seems to be broken on i830 */
1045 		i915->display.gmbus.bus[pin] = bus;
1061 	if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
1062 			!i915->display.gmbus.bus[pin]))
1065 	return &i915->display.gmbus.bus[pin]->adapter;
1073 	mutex_lock(&i915->display.gmbus.mutex);
1081 	mutex_unlock(&i915->display.gmbus.mutex);
1095 	for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
1098 		bus = i915->display.gmbus.bus[pin];
1105 		i915->display.gmbus.bus[pin] = NULL;
1111 	wake_up_all(&i915->display.gmbus.wait_queue);