Lines Matching refs:mg_pll_bias
2979 pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
3030 pll_state->mg_pll_bias =
3050 pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
3070 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
3071 m2_frac = pll_state->mg_pll_bias &
3441 hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));
3454 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3518 hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port));
3519 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
3685 hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
3747 val |= hw_state->mg_pll_bias;
3957 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
3968 hw_state->mg_pll_bias,