Lines Matching refs:temp
1920 u32 temp;
1965 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6));
1966 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1967 temp &= ~PORT_PLL_INT_COEFF_MASK;
1968 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1969 temp |= pll->state.hw_state.pll6;
1970 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6), temp);
1979 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10));
1980 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1981 temp &= ~PORT_PLL_DCO_AMP_MASK;
1982 temp |= pll->state.hw_state.pll10;
1983 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10), temp);
1986 temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch));
1987 temp |= PORT_PLL_RECALIBRATE;
1988 intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp);
1989 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1990 temp |= pll->state.hw_state.ebb4;
1991 intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp);
2002 temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch));
2003 temp |= DCC_DELAY_RANGE_2;
2004 intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
2011 temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch));
2012 temp &= ~LANE_STAGGER_MASK;
2013 temp &= ~LANESTAGGER_STRAP_OVRD;
2014 temp |= pll->state.hw_state.pcsdw12;
2015 intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);