i915/display/intel_dp.c

142 	int i, max_rate;
158 	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
161 		max_rate = min(max_rate, max_lttpr_rate);
164 		if (dp_rates[i] > max_rate)
255 /* Get length of rates array potentially limited by max_rate. */
256 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
262 		if (rates[len - i - 1] <= max_rate)
269 /* Get length of common rates array potentially limited by max_rate. */
271 					  int max_rate)
274 				       intel_dp->num_common_rates, max_rate);
445 	int max_rate;
447 	max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
453 		if (max_rate && edp_max_rate)
454 			max_rate = min(max_rate, edp_max_rate);
456 			max_rate = edp_max_rate;
459 	return max_rate;
489 	int size, max_rate = 0, vbt_max_rate;
498 		max_rate = mtl_max_source_rate(intel_dp);
503 			max_rate = dg2_max_source_rate(intel_dp);
506 			max_rate = 810000;
508 			max_rate = ehl_max_source_rate(intel_dp);
510 			max_rate = icl_max_source_rate(intel_dp);
527 	if (max_rate && vbt_max_rate)
528 		max_rate = min(max_rate, vbt_max_rate);
530 		max_rate = vbt_max_rate;
532 	if (max_rate)
533 		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
620 	int mode_rate, max_rate;
623 	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
624 	if (mode_rate > max_rate)
1127 	int max_rate, mode_rate, max_lanes, max_link_clock;
1166 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1214 	if (mode_rate > max_rate && !dsc)
1450 				limits->min_rate = limits->max_rate =
1501 			    link_rate > limits->max_rate)
1709 	pipe_config->port_clock = limits->max_rate;
1824 	limits.max_rate = intel_dp_max_link_rate(intel_dp);
1842 		limits.min_rate = limits.max_rate;
1849 		    limits.max_lane_count, limits.max_rate,