i915/display/intel_display.c

663 	 * are blocked if the memory self-refresh mode is active at that
665 	 * first the self-refresh mode. The self-refresh enable bit in turn
1080 	 * are blocked if the memory self-refresh mode is active at that
1082 	 * first the self-refresh mode. The self-refresh enable bit in turn
2116 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2119 	mode->hdisplay = timings->crtc_hdisplay;
2120 	mode->htotal = timings->crtc_htotal;
2121 	mode->hsync_start = timings->crtc_hsync_start;
2122 	mode->hsync_end = timings->crtc_hsync_end;
2124 	mode->vdisplay = timings->crtc_vdisplay;
2125 	mode->vtotal = timings->crtc_vtotal;
2126 	mode->vsync_start = timings->crtc_vsync_start;
2127 	mode->vsync_end = timings->crtc_vsync_end;
2129 	mode->flags = timings->flags;
2130 	mode->type = DRM_MODE_TYPE_DRIVER;
2132 	mode->clock = timings->crtc_clock;
2134 	drm_mode_set_name(mode);
2151 					   struct drm_display_mode *mode)
2158 	mode->crtc_clock /= num_pipes;
2159 	mode->crtc_hdisplay /= num_pipes;
2160 	mode->crtc_hblank_start /= num_pipes;
2161 	mode->crtc_hblank_end /= num_pipes;
2162 	mode->crtc_hsync_start /= num_pipes;
2163 	mode->crtc_hsync_end /= num_pipes;
2164 	mode->crtc_htotal /= num_pipes;
2168 					  struct drm_display_mode *mode)
2178 	 * timings, but full mode for everything else.
2182 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2183 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2184 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2185 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2186 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2187 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2188 	mode->crtc_clock *= n;
2193 	struct drm_display_mode *mode = &crtc_state->hw.mode;
2213 	/* Populate the "user" mode with full numbers */
2214 	drm_mode_copy(mode, pipe_mode);
2215 	intel_mode_from_crtc_timings(mode, mode);
2216 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2218 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2259 	 * - DVO ganged mode
2260 	 * - LVDS dual channel mode
2308 		 * Enable double wide mode when the dot clock
2502 	/* We need to be careful not to changed the adjusted mode, for otherwise
2860 		/* We support 4:2:0 in full blend mode only */
3657 		/* XXX: this works for video mode only */
3834 /* Returns the clock of the currently programmed mode of the given pipe. */
3879 				    "Unknown DPLL mode %08x in programmed "
3880 				    "mode\n", (int)(dpll & DPLL_MODE_MASK));
3970 /* Returns the currently programmed mode of the given encoder. */
3976 	struct drm_display_mode *mode;
3985 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3986 	if (!mode)
3991 		kfree(mode);
3997 		kfree(mode);
4003 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4007 	return mode;
4520 	drm_mode_copy(&crtc_state->hw.mode,
4521 		      &crtc_state->uapi.mode);
4581 	drm_mode_copy(&slave_crtc_state->hw.mode,
4582 		      &master_crtc_state->hw.mode);
4682 	 * is stored in the crtc timings. We use the requested mode to do this
4683 	 * computation to clearly distinguish it from the adjusted mode, which
4686 	drm_mode_get_hv_timing(&crtc_state->hw.mode,
4726 	/* Pass our mode to the connectors and the CRTC to give them a chance to
4728 	 * a chance to reject the mode entirely.
4749 	 * done afterwards in case the encoder adjusts the mode. */
5475  * This implements the workaround described in the "notes" section of the mode
6110 				    "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6471 	 * that in compute_mode_changes we check the native mode (not the pfit
6472 	 * mode) to see if we can flip rather than do a full mode set. In the
7611 				      const struct drm_display_mode *mode)
7619 	 * of DBLSCAN modes to the output's mode list when they detect
7620 	 * the scaling mode property on the connector. And they don't
7627 	 * as we never want such modes on the connector's mode list.
7630 	if (mode->vscan > 1)
7633 	if (mode->flags & DRM_MODE_FLAG_HSKEW)
7636 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7641 	if (mode->flags & (DRM_MODE_FLAG_BCAST |
7650 	if (mode->clock > max_dotclock(dev_priv))
7677 	if (mode->hdisplay > hdisplay_max ||
7678 	    mode->hsync_start > htotal_max ||
7679 	    mode->hsync_end > htotal_max ||
7680 	    mode->htotal > htotal_max)
7683 	if (mode->vdisplay > vdisplay_max ||
7684 	    mode->vsync_start > vtotal_max ||
7685 	    mode->vsync_end > vtotal_max ||
7686 	    mode->vtotal > vtotal_max)
7693 						     const struct drm_display_mode *mode)
7700 		if (mode->hdisplay < 64 ||
7701 		    mode->htotal - mode->hdisplay < 32)
7704 		if (mode->vtotal - mode->vdisplay < 5)
7707 		if (mode->htotal - mode->hdisplay < 32)
7710 		if (mode->vtotal - mode->vdisplay < 3)
7719 	    mode->hsync_start == mode->hdisplay)
7727 				const struct drm_display_mode *mode,
7752 	if (mode->hdisplay > plane_width_max)
7755 	if (mode->vdisplay > plane_height_max)
7941 	 * Apparently we need to have VGA mode enabled prior to changing