i915/display/intel_ddi.c

389 	u32 temp;
396 	temp = DP_MSA_MISC_SYNC_CLOCK;
400 		temp |= DP_MSA_MISC_6_BPC;
403 		temp |= DP_MSA_MISC_8_BPC;
406 		temp |= DP_MSA_MISC_10_BPC;
409 		temp |= DP_MSA_MISC_12_BPC;
421 		temp |= DP_MSA_MISC_COLOR_CEA_RGB;
429 		temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
438 		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
440 	intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
480 	u32 temp;
483 	temp = TRANS_DDI_FUNC_ENABLE;
485 		temp |= TGL_TRANS_DDI_SELECT_PORT(port);
487 		temp |= TRANS_DDI_SELECT_PORT(port);
494 		temp |= TRANS_DDI_BPC_6;
497 		temp |= TRANS_DDI_BPC_8;
500 		temp |= TRANS_DDI_BPC_10;
503 		temp |= TRANS_DDI_BPC_12;
508 		temp |= TRANS_DDI_PVSYNC;
510 		temp |= TRANS_DDI_PHSYNC;
523 				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
525 				temp |= TRANS_DDI_EDP_INPUT_A_ON;
528 			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
531 			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
538 			temp |= TRANS_DDI_MODE_SELECT_HDMI;
540 			temp |= TRANS_DDI_MODE_SELECT_DVI;
543 			temp |= TRANS_DDI_HDMI_SCRAMBLING;
545 			temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
547 			temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
549 		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
550 		temp |= (crtc_state->fdi_lanes - 1) << 1;
553 			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
555 			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
556 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
564 			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
567 		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
568 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
576 		temp |= TRANS_DDI_PORT_SYNC_ENABLE |
580 	return temp;
3515 	u32 temp;
3517 	temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3519 	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3522 		temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3525 		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3528 		temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3531 		temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3534 		temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3538 	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3660 	u32 temp, flags = 0;
3662 	temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3663 	if (temp & TRANS_DDI_PHSYNC)
3667 	if (temp & TRANS_DDI_PVSYNC)
3674 	switch (temp & TRANS_DDI_BPC_MASK) {
3691 	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3701 		if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3703 		if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3710 				((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3720 			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3756 			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3760 					REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);