i915/display/intel_ddi.c

1113 	int n_entries, ln;
1139 	for (ln = 0; ln < 4; ln++) {
1140 		int level = intel_ddi_level(encoder, crtc_state, ln);
1142 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1151 	for (ln = 0; ln < 4; ln++) {
1152 		int level = intel_ddi_level(encoder, crtc_state, ln);
1154 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1162 	for (ln = 0; ln < 4; ln++) {
1163 		int level = intel_ddi_level(encoder, crtc_state, ln);
1165 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1177 	int ln;
1198 	for (ln = 0; ln < 4; ln++) {
1199 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1201 			     icl_combo_phy_loadgen_select(crtc_state, ln));
1228 	int n_entries, ln;
1237 	for (ln = 0; ln < 2; ln++) {
1238 		intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1240 		intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1245 	for (ln = 0; ln < 2; ln++) {
1248 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1250 		intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1254 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1256 		intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1262 	for (ln = 0; ln < 2; ln++) {
1265 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1267 		intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1274 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1276 		intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1291 	for (ln = 0; ln < 2; ln++) {
1292 		intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1298 	for (ln = 0; ln < 2; ln++) {
1299 		intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1306 		intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1315 	for (ln = 0; ln < 2; ln++) {
1316 		intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1318 		intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1329 	int n_entries, ln;
1338 	for (ln = 0; ln < 2; ln++) {
1341 		intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1343 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1345 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
1353 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1355 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
1363 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1370 				if (ln == 0) {
1382 			intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
3406 	int ln;
3408 	for (ln = 0; ln < 2; ln++)
3409 		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);