Lines Matching defs:cdclk
78 u8 (*calc_voltage_level)(int cdclk);
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
101 int cdclk)
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
109 cdclk_config->cdclk = 133333;
115 cdclk_config->cdclk = 200000;
121 cdclk_config->cdclk = 266667;
127 cdclk_config->cdclk = 333333;
133 cdclk_config->cdclk = 400000;
139 cdclk_config->cdclk = 450000;
154 cdclk_config->cdclk = 133333;
168 cdclk_config->cdclk = 200000;
171 cdclk_config->cdclk = 250000;
174 cdclk_config->cdclk = 133333;
179 cdclk_config->cdclk = 266667;
193 cdclk_config->cdclk = 133333;
199 cdclk_config->cdclk = 333333;
203 cdclk_config->cdclk = 190000;
217 cdclk_config->cdclk = 133333;
223 cdclk_config->cdclk = 320000;
227 cdclk_config->cdclk = 200000;
340 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
348 cdclk_config->cdclk = 190476;
361 cdclk_config->cdclk = 266667;
364 cdclk_config->cdclk = 333333;
367 cdclk_config->cdclk = 444444;
370 cdclk_config->cdclk = 200000;
377 cdclk_config->cdclk = 133333;
380 cdclk_config->cdclk = 166667;
419 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
427 cdclk_config->cdclk = 200000;
447 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
450 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
456 cdclk_config->cdclk = 222222;
468 cdclk_config->cdclk = 800000;
470 cdclk_config->cdclk = 450000;
472 cdclk_config->cdclk = 450000;
474 cdclk_config->cdclk = 337500;
476 cdclk_config->cdclk = 540000;
499 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
502 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
504 else if (cdclk >= 266667)
514 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
527 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
553 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
585 int cdclk = cdclk_config->cdclk;
589 switch (cdclk) {
597 MISSING_CASE(cdclk);
625 if (cdclk == 400000) {
629 cdclk) - 1;
631 /* adjust cdclk divider */
652 if (cdclk == 400000)
674 int cdclk = cdclk_config->cdclk;
678 switch (cdclk) {
685 MISSING_CASE(cdclk);
730 static u8 bdw_calc_voltage_level(int cdclk)
732 switch (cdclk) {
752 cdclk_config->cdclk = 800000;
754 cdclk_config->cdclk = 450000;
756 cdclk_config->cdclk = 450000;
758 cdclk_config->cdclk = 540000;
760 cdclk_config->cdclk = 337500;
762 cdclk_config->cdclk = 675000;
769 bdw_calc_voltage_level(cdclk_config->cdclk);
772 static u32 bdw_cdclk_freq_sel(int cdclk)
774 switch (cdclk) {
776 MISSING_CASE(cdclk);
793 int cdclk = cdclk_config->cdclk;
802 "trying to change cdclk frequency with cdclk not enabled\n"))
808 "failed to inform pcode about cdclk change\n");
824 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
837 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
865 static u8 skl_calc_voltage_level(int cdclk)
867 if (cdclk > 540000)
869 else if (cdclk > 450000)
871 else if (cdclk > 337500)
925 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
935 cdclk_config->cdclk = 432000;
938 cdclk_config->cdclk = 308571;
941 cdclk_config->cdclk = 540000;
944 cdclk_config->cdclk = 617143;
953 cdclk_config->cdclk = 450000;
956 cdclk_config->cdclk = 337500;
959 cdclk_config->cdclk = 540000;
962 cdclk_config->cdclk = 675000;
976 skl_calc_voltage_level(cdclk_config->cdclk);
980 static int skl_cdclk_decimal(int cdclk)
982 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1031 dev_priv->display.cdclk.hw.vco = vco;
1045 dev_priv->display.cdclk.hw.vco = 0;
1049 int cdclk, int vco)
1051 switch (cdclk) {
1054 cdclk != dev_priv->display.cdclk.hw.bypass);
1075 int cdclk = cdclk_config->cdclk;
1097 "Failed to inform PCU about cdclk change (%d)\n", ret);
1101 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
1103 if (dev_priv->display.cdclk.hw.vco != 0 &&
1104 dev_priv->display.cdclk.hw.vco != vco)
1109 if (dev_priv->display.cdclk.hw.vco != vco) {
1112 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1121 if (dev_priv->display.cdclk.hw.vco != vco)
1128 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1156 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1159 if (dev_priv->display.cdclk.hw.vco == 0 ||
1160 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
1171 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
1177 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1179 /* force cdclk programming */
1180 dev_priv->display.cdclk.hw.cdclk = 0;
1182 dev_priv->display.cdclk.hw.vco = -1;
1191 if (dev_priv->display.cdclk.hw.cdclk != 0 &&
1192 dev_priv->display.cdclk.hw.vco != 0) {
1199 dev_priv->display.cdclk.hw.vco);
1203 cdclk_config = dev_priv->display.cdclk.hw;
1208 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1209 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1216 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
1218 cdclk_config.cdclk = cdclk_config.bypass;
1220 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1226 u32 cdclk;
1234 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1235 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1236 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1237 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1243 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1244 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1245 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1250 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1251 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1252 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1253 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1254 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1255 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1257 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1258 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1259 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1260 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1261 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1262 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1264 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1265 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1266 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1267 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1268 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1269 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1274 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1275 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1276 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1277 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1278 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1279 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1281 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1282 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1283 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1284 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1285 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1286 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1288 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1289 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1290 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1291 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1292 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1293 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1298 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1299 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1300 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1302 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1303 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1304 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1306 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1307 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1308 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1313 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1314 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1315 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1316 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1317 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1319 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1320 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1321 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1322 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1323 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1325 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1326 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1327 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1328 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1329 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1334 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1335 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1336 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1337 { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
1338 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1339 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1341 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1342 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1343 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1344 { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
1345 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1346 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1348 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1349 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1350 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1351 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
1352 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1353 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1358 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
1359 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
1360 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
1361 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
1362 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
1363 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
1364 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
1365 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
1366 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
1367 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
1368 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1369 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1370 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1375 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1376 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1377 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
1378 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
1379 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
1380 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
1386 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1390 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1391 table[i].cdclk >= min_cdclk)
1392 return table[i].cdclk;
1395 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1396 min_cdclk, dev_priv->display.cdclk.hw.ref);
1400 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1402 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1405 if (cdclk == dev_priv->display.cdclk.hw.bypass)
1409 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1410 table[i].cdclk == cdclk)
1411 return dev_priv->display.cdclk.hw.ref * table[i].ratio;
1413 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1414 cdclk, dev_priv->display.cdclk.hw.ref);
1418 static u8 bxt_calc_voltage_level(int cdclk)
1420 return DIV_ROUND_UP(cdclk, 25000);
1423 static u8 icl_calc_voltage_level(int cdclk)
1425 if (cdclk > 556800)
1427 else if (cdclk > 312000)
1433 static u8 ehl_calc_voltage_level(int cdclk)
1435 if (cdclk > 326400)
1437 else if (cdclk > 312000)
1439 else if (cdclk > 180000)
1445 static u8 tgl_calc_voltage_level(int cdclk)
1447 if (cdclk > 556800)
1449 else if (cdclk > 326400)
1451 else if (cdclk > 312000)
1457 static u8 rplu_calc_voltage_level(int cdclk)
1459 if (cdclk > 556800)
1461 else if (cdclk > 480000)
1463 else if (cdclk > 312000)
1542 cdclk_config->cdclk = cdclk_config->bypass;
1576 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1579 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1588 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
1600 dev_priv->display.cdclk.hw.vco = 0;
1605 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1617 dev_priv->display.cdclk.hw.vco = vco;
1629 dev_priv->display.cdclk.hw.vco = 0;
1634 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1647 dev_priv->display.cdclk.hw.vco = vco;
1652 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1671 dev_priv->display.cdclk.hw.vco = vco;
1695 int cdclk, int vco)
1697 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1698 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1701 cdclk != dev_priv->display.cdclk.hw.bypass);
1716 int cdclk)
1718 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1721 if (cdclk == dev_priv->display.cdclk.hw.bypass)
1725 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1726 table[i].cdclk == cdclk)
1729 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1730 cdclk, dev_priv->display.cdclk.hw.ref);
1737 if (i915->display.cdclk.hw.vco != 0 &&
1738 i915->display.cdclk.hw.vco != vco)
1741 if (i915->display.cdclk.hw.vco != vco)
1747 if (i915->display.cdclk.hw.vco != 0 &&
1748 i915->display.cdclk.hw.vco != vco)
1751 if (i915->display.cdclk.hw.vco != vco)
1799 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
1800 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
1812 * - If moving to a higher cdclk, the desired action is squashing.
1813 * The mid cdclk config should have the new (squash) waveform.
1814 * - If moving to a lower cdclk, the desired action is crawling.
1815 * The mid cdclk config should have the new vco.
1826 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
1831 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
1832 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
1833 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
1834 i915->display.cdclk.max_cdclk_freq);
1835 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
1844 dev_priv->display.cdclk.hw.vco > 0 &&
1852 int cdclk = cdclk_config->cdclk;
1858 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
1859 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
1860 if (dev_priv->display.cdclk.hw.vco != vco)
1871 waveform = cdclk_squash_waveform(dev_priv, cdclk);
1876 clock = cdclk;
1883 skl_cdclk_decimal(cdclk);
1890 cdclk >= 500000)
1903 int cdclk = cdclk_config->cdclk;
1930 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1931 ret, cdclk);
1935 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
1966 ret, cdclk);
1977 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
1983 int cdclk, clock, vco;
1986 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1988 if (dev_priv->display.cdclk.hw.vco == 0 ||
1989 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
2006 /* Make sure this is a legal cdclk value for the platform */
2007 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
2008 if (cdclk != dev_priv->display.cdclk.hw.cdclk)
2011 /* Make sure the VCO is correct for the cdclk */
2012 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2013 if (vco != dev_priv->display.cdclk.hw.vco)
2016 expected = skl_cdclk_decimal(cdclk);
2018 /* Figure out what CD2X divider we should be using for this cdclk */
2020 clock = dev_priv->display.cdclk.hw.vco / 2;
2022 clock = dev_priv->display.cdclk.hw.cdclk;
2025 dev_priv->display.cdclk.hw.vco);
2032 dev_priv->display.cdclk.hw.cdclk >= 500000)
2040 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
2042 /* force cdclk programming */
2043 dev_priv->display.cdclk.hw.cdclk = 0;
2046 dev_priv->display.cdclk.hw.vco = -1;
2055 if (dev_priv->display.cdclk.hw.cdclk != 0 &&
2056 dev_priv->display.cdclk.hw.vco != 0)
2059 cdclk_config = dev_priv->display.cdclk.hw;
2066 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
2067 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
2069 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2076 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
2078 cdclk_config.cdclk = cdclk_config.bypass;
2081 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2090 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2133 old_waveform = cdclk_squash_waveform(i915, a->cdclk);
2134 new_waveform = cdclk_squash_waveform(i915, b->cdclk);
2153 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2154 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2175 return a->cdclk != b->cdclk &&
2194 return a->cdclk != b->cdclk ||
2227 return a->cdclk != b->cdclk &&
2253 context, cdclk_config->cdclk, cdclk_config->vco,
2261 u16 cdclk,
2271 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2305 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
2308 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
2322 * Lock aux/gmbus while we change cdclk in case those
2323 * functions use cdclk. Not all platforms/ports do,
2352 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
2353 "cdclk state doesn't match!\n")) {
2354 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
2366 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2378 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2389 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2400 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2411 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2417 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2426 cdclk = new_cdclk_state->actual.cdclk;
2437 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2470 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2512 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2564 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2570 * there may be audio corruption or screen corruption." This cdclk
2594 * "For DP audio configuration, cdclk frequency shall be set to
2627 * cannot be higher than the VDSC clock (cdclk)
2629 * VDSC clock(cdclk) * 2 and so on.
2655 dev_priv->display.cdclk.max_cdclk_freq));
2720 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
2722 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2723 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
2783 int min_cdclk, cdclk;
2789 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2791 cdclk_state->logical.cdclk = cdclk;
2793 vlv_calc_voltage_level(dev_priv, cdclk);
2796 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2798 cdclk_state->actual.cdclk = cdclk;
2800 vlv_calc_voltage_level(dev_priv, cdclk);
2810 int min_cdclk, cdclk;
2816 cdclk = bdw_calc_cdclk(min_cdclk);
2818 cdclk_state->logical.cdclk = cdclk;
2820 bdw_calc_voltage_level(cdclk);
2823 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2825 cdclk_state->actual.cdclk = cdclk;
2827 bdw_calc_voltage_level(cdclk);
2856 * clock for eDP. This will affect cdclk as well.
2874 int min_cdclk, cdclk, vco;
2882 cdclk = skl_calc_cdclk(min_cdclk, vco);
2885 cdclk_state->logical.cdclk = cdclk;
2887 skl_calc_voltage_level(cdclk);
2890 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
2893 cdclk_state->actual.cdclk = cdclk;
2895 skl_calc_voltage_level(cdclk);
2907 int min_cdclk, min_voltage_level, cdclk, vco;
2917 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2918 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2921 cdclk_state->logical.cdclk = cdclk;
2924 intel_cdclk_calc_voltage_level(dev_priv, cdclk));
2927 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2928 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2931 cdclk_state->actual.cdclk = cdclk;
2933 intel_cdclk_calc_voltage_level(dev_priv, cdclk);
2946 * We can't change the cdclk frequency, but we still want to
2948 * the actual cdclk frequency.
2988 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
3007 * planes are part of the state. We can now compute the minimum cdclk
3038 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
3121 "Can change cdclk via crawling and squashing\n");
3126 "Can change cdclk via squashing\n");
3131 "Can change cdclk via crawling\n");
3136 "Can change cdclk cd2x divider with pipe %c active\n",
3140 /* All pipes must be switched off while we change the cdclk. */
3148 "Modeset required for cdclk change\n");
3152 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3153 new_cdclk_state->logical.cdclk,
3154 new_cdclk_state->actual.cdclk);
3165 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
3191 if (dev_priv->display.cdclk.hw.ref == 24000)
3192 dev_priv->display.cdclk.max_cdclk_freq = 552000;
3194 dev_priv->display.cdclk.max_cdclk_freq = 556800;
3196 if (dev_priv->display.cdclk.hw.ref == 24000)
3197 dev_priv->display.cdclk.max_cdclk_freq = 648000;
3199 dev_priv->display.cdclk.max_cdclk_freq = 652800;
3201 dev_priv->display.cdclk.max_cdclk_freq = 316800;
3203 dev_priv->display.cdclk.max_cdclk_freq = 624000;
3212 * Use the lower (vco 8640) cdclk values as a
3225 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3234 dev_priv->display.cdclk.max_cdclk_freq = 450000;
3236 dev_priv->display.cdclk.max_cdclk_freq = 450000;
3238 dev_priv->display.cdclk.max_cdclk_freq = 540000;
3240 dev_priv->display.cdclk.max_cdclk_freq = 675000;
3242 dev_priv->display.cdclk.max_cdclk_freq = 320000;
3244 dev_priv->display.cdclk.max_cdclk_freq = 400000;
3246 /* otherwise assume cdclk is fixed */
3247 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
3253 dev_priv->display.cdclk.max_cdclk_freq);
3267 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
3272 * of cdclk that generates 4MHz reference clock freq which is used to
3273 * generate GMBus clock. This will vary with the cdclk freq.
3277 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
3428 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
3429 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
3595 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3596 dev_priv->display.cdclk.table = mtl_cdclk_table;
3598 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3599 dev_priv->display.cdclk.table = dg2_cdclk_table;
3603 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
3604 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3606 dev_priv->display.cdclk.table = rplu_cdclk_table;
3607 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
3609 dev_priv->display.cdclk.table = adlp_cdclk_table;
3610 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3613 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3614 dev_priv->display.cdclk.table = rkl_cdclk_table;
3616 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3617 dev_priv->display.cdclk.table = icl_cdclk_table;
3619 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
3620 dev_priv->display.cdclk.table = icl_cdclk_table;
3622 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
3623 dev_priv->display.cdclk.table = icl_cdclk_table;
3625 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
3627 dev_priv->display.cdclk.table = glk_cdclk_table;
3629 dev_priv->display.cdclk.table = bxt_cdclk_table;
3631 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
3633 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
3635 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
3637 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
3639 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
3641 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3643 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
3645 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
3647 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3649 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
3651 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3653 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
3655 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3657 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
3659 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3661 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
3663 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
3665 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
3667 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
3669 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
3671 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3674 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
3676 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;