swsmu/smu13/smu_v13_0_6_ppt.c

387 					     uint32_t *min, uint32_t *max)
430 		if (max)
431 			*max = clock_limit;
446 	if (max) {
449 				smu, SMU_MSG_GetMaxGfxclkFrequency, max);
452 				smu, SMU_MSG_GetMaxDpmFreq, param, max);
516 		 * Get min/max values from FW.
529 		dpm_table->max = dpm_table->dpm_levels[1].value;
535 		dpm_table->max = dpm_table->dpm_levels[0].value;
555 		dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
602 	pstate_table->gfxclk_pstate.peak = gfx_table->max;
604 	pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
607 	pstate_table->uclk_pstate.peak = mem_table->max;
609 	pstate_table->uclk_pstate.curr.max = mem_table->max;
612 	pstate_table->socclk_pstate.peak = soc_table->max;
614 	pstate_table->socclk_pstate.curr.max = soc_table->max;
735 	/* This is the max of all VRs and not just SOC VR.
820 		max_clk = pstate_table->gfxclk_pstate.curr.max;
1006 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1018 			(max ? SMU_MSG_SetSoftMaxGfxClk :
1024 				max ? "max" : "min");
1035 			(max ? SMU_MSG_SetSoftMaxByFreq :
1041 				max ? "max" : "min");
1051 			(max ? SMU_MSG_SetSoftMaxByFreq :
1057 				max ? "max" : "min");
1081 				"Clock level specified %d is over max allowed %d\n",
1101 				"Failed to upload dpm max level to highest!\n");
1418 						       uint32_t max)
1423 					      max & 0xffff, NULL);
1447 		pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1456 		    (gfx_table->max == pstate_table->gfxclk_pstate.curr.max))
1460 			smu, gfx_table->min, gfx_table->max);
1465 		pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1478 						   uint32_t min, uint32_t max)
1496 		if (min >= max) {
1503 		    (max == pstate_table->gfxclk_pstate.curr.max))
1506 		ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min, max);
1509 			pstate_table->gfxclk_pstate.curr.max = max;
1516 		if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1517 		    (max > dpm_context->dpm_tables.gfx_table.max)) {
1520 				"Invalid max frequency %d MHz specified for determinism\n",
1521 				max);
1525 		/* Restore default min/max clocks and enable determinism */
1527 		max_clk = dpm_context->dpm_tables.gfx_table.max;
1533 				smu, SMU_MSG_EnableDeterminism, max, NULL);
1537 					max);
1540 				pstate_table->gfxclk_pstate.curr.max = max;
1586 			if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1591 					dpm_context->dpm_tables.gfx_table.max);
1592 				pstate_table->gfxclk_pstate.custom.max =
1593 					pstate_table->gfxclk_pstate.curr.max;
1597 			pstate_table->gfxclk_pstate.custom.max = input[1];
1610 			max_clk = dpm_context->dpm_tables.gfx_table.max;
1626 			if (!pstate_table->gfxclk_pstate.custom.max)
1627 				pstate_table->gfxclk_pstate.custom.max =
1628 					pstate_table->gfxclk_pstate.curr.max;
1631 			max_clk = pstate_table->gfxclk_pstate.custom.max;
1985 	/* Reports max temperature of all voltage rails */
2072 	/* This is similar to FLR, wait till max FLR timeout */