swsmu/smu11/sienna_cichlid_ppt.c

943 	dpm_table = &dpm_context->dpm_tables.soc_table;
962 	dpm_table = &dpm_context->dpm_tables.gfx_table;
980 	dpm_table = &dpm_context->dpm_tables.uclk_table;
998 	dpm_table = &dpm_context->dpm_tables.fclk_table;
1020 		dpm_table = &dpm_context->dpm_tables.vclk_table;
1042 		dpm_table = &dpm_context->dpm_tables.dclk_table;
1061 	dpm_table = &dpm_context->dpm_tables.dcef_table;
1079 	dpm_table = &dpm_context->dpm_tables.pixel_table;
1097 	dpm_table = &dpm_context->dpm_tables.display_table;
1115 	dpm_table = &dpm_context->dpm_tables.phy_table;
1342 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1343 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1344 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1345 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1346 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1347 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1348 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1349 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1350 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1351 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1353 					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1354 					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1479 				&dpm_context->dpm_tables.gfx_table;
1481 				&dpm_context->dpm_tables.uclk_table;
1483 				&dpm_context->dpm_tables.soc_table;
2094 	struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;