Lines Matching defs:od_settings

399 	 * smu->od_settings just points to the actual overdrive_table
401 smu->od_settings = &powerplay_table->overdrive_table;
1272 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1357 if (!smu->od_enabled || !od_table || !od_settings)
1359 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1365 if (!smu->od_enabled || !od_table || !od_settings)
1367 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1372 if (!smu->od_enabled || !od_table || !od_settings)
1374 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1397 if (!smu->od_enabled || !od_table || !od_settings)
1401 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1402 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1404 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1410 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1411 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1417 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1418 navi10_od_setting_get_range(od_settings,
1424 navi10_od_setting_get_range(od_settings,
1430 navi10_od_setting_get_range(od_settings,
1436 navi10_od_setting_get_range(od_settings,
1442 navi10_od_setting_get_range(od_settings,
1448 navi10_od_setting_get_range(od_settings,
1479 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1556 if (!smu->od_enabled || !od_table || !od_settings)
1558 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1565 if (!smu->od_enabled || !od_table || !od_settings)
1567 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1573 if (!smu->od_enabled || !od_table || !od_settings)
1575 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1598 if (!smu->od_enabled || !od_table || !od_settings)
1602 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1603 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1605 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1611 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1612 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1618 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1619 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1623 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1627 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1631 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1635 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1639 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
2342 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2363 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2569 struct smu_11_0_overdrive_table *od_settings;
2579 if (!smu->od_settings) {
2584 od_settings = smu->od_settings;
2588 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2627 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2634 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2647 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2677 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2714 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2719 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);