Lines Matching defs:table
449 SMU75_Discrete_DpmTable *table)
459 table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
462 table->SmioTable2.Pattern[level].Smio =
464 table->Smio[level] |=
467 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
469 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
476 struct SMU75_Discrete_DpmTable *table)
487 table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
489 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
491 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
495 table->SmioMask1 = data->vddci_voltage_table.mask_low;
501 struct SMU75_Discrete_DpmTable *table)
512 * We are populating vddc CAC data to BapmVddc table
518 table->BapmVddcVidLoSidd[count] =
520 table->BapmVddcVidHiSidd[count] =
522 table->BapmVddcVidHiSidd2[count] =
530 struct SMU75_Discrete_DpmTable *table)
532 vegam_populate_smc_vddci_table(hwmgr, table);
533 vegam_populate_smc_mvdd_table(hwmgr, table);
534 vegam_populate_cac_table(hwmgr, table);
563 struct SMU75_Discrete_DpmTable *table)
565 return vegam_populate_ulv_level(hwmgr, &table->Ulv);
569 struct SMU75_Discrete_DpmTable *table)
580 table->LinkLevel[i].PcieGenSpeed =
582 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
584 table->LinkLevel[i].EnabledForActivity = 1;
585 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
586 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
587 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
610 /* clock - voltage dependency table is empty table */
644 /* sclk is bigger than max sclk in the dependence table */
670 SMU75_Discrete_DpmTable *table)
681 table->SclkFcwRangeTable[i].vco_setting =
683 table->SclkFcwRangeTable[i].postdiv =
685 table->SclkFcwRangeTable[i].fcw_pcc =
688 table->SclkFcwRangeTable[i].fcw_trans_upper =
690 table->SclkFcwRangeTable[i].fcw_trans_lower =
693 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
694 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
695 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
706 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
707 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
708 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
710 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
711 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
713 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
714 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
715 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
723 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
760 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
762 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
770 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
779 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
781 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
829 "VDDC engine clock dependency table",
956 /* level count will send to smc once at init smc table and never change */
997 "VDDC voltage dependency table", return result);
1040 /* populate MCLK dpm table to SMU7 */
1078 /* level count will send to smc once at init smc table and never change */
1111 SMU75_Discrete_DpmTable *table)
1121 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1129 &table->ACPILevel.MinVoltage, &mvdd);
1136 &(table->ACPILevel.SclkSetting));
1141 table->ACPILevel.DeepSleepDivId = 0;
1142 table->ACPILevel.CcPwrDynRm = 0;
1143 table->ACPILevel.CcPwrDynRm1 = 0;
1145 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1146 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1150 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1151 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1152 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1153 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1154 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1155 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1156 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1157 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1158 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1159 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1163 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1166 table->MemoryACPILevel.MclkFrequency,
1167 &table->MemoryACPILevel.MinVoltage, &mvdd);
1174 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1176 table->MemoryACPILevel.MinMvdd = 0;
1178 table->MemoryACPILevel.StutterEnable = false;
1180 table->MemoryACPILevel.EnabledForThrottle = 0;
1181 table->MemoryACPILevel.EnabledForActivity = 0;
1182 table->MemoryACPILevel.UpHyst = 0;
1183 table->MemoryACPILevel.DownHyst = 100;
1184 table->MemoryACPILevel.VoltageDownHyst = 0;
1185 table->MemoryACPILevel.ActivityLevel =
1188 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1189 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1195 SMU75_Discrete_DpmTable *table)
1207 table->VceLevelCount = (uint8_t)(mm_table->count);
1208 table->VceBootLevel = 0;
1210 for (count = 0; count < table->VceLevelCount; count++) {
1211 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1212 table->VceLevel[count].MinVoltage = 0;
1213 table->VceLevel[count].MinVoltage |=
1225 table->VceLevel[count].MinVoltage |=
1227 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1231 table->VceLevel[count].Frequency, ÷rs);
1236 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1238 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1239 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1308 struct SMU75_Discrete_DpmTable *table)
1320 table->UvdLevelCount = (uint8_t)(mm_table->count);
1321 table->UvdBootLevel = 0;
1323 for (count = 0; count < table->UvdLevelCount; count++) {
1324 table->UvdLevel[count].MinVoltage = 0;
1325 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1326 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1327 table->UvdLevel[count].MinVoltage |=
1338 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1339 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1343 table->UvdLevel[count].VclkFrequency, ÷rs);
1347 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1350 table->UvdLevel[count].DclkFrequency, ÷rs);
1354 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1356 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1357 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1358 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1365 struct SMU75_Discrete_DpmTable *table)
1370 table->GraphicsBootLevel = 0;
1371 table->MemoryBootLevel = 0;
1373 /* find boot level from dpm table */
1376 (uint32_t *)&(table->GraphicsBootLevel));
1382 (uint32_t *)&(table->MemoryBootLevel));
1387 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1389 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1391 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1394 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1395 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1396 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1443 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1453 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1454 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1460 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
1462 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
1464 table->FanGainEdge = PP_HOST_TO_SMC_US(
1466 table->FanGainHotspot = PP_HOST_TO_SMC_US(
1475 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
1476 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
1566 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1584 table->BTCGB_VDROOP_TABLE[0].a0 =
1586 table->BTCGB_VDROOP_TABLE[0].a1 =
1588 table->BTCGB_VDROOP_TABLE[0].a2 =
1590 table->BTCGB_VDROOP_TABLE[1].a0 =
1592 table->BTCGB_VDROOP_TABLE[1].a1 =
1594 table->BTCGB_VDROOP_TABLE[1].a2 =
1596 table->AVFSGB_FUSE_TABLE[0].m1 =
1598 table->AVFSGB_FUSE_TABLE[0].m2 =
1600 table->AVFSGB_FUSE_TABLE[0].b =
1602 table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;
1603 table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;
1604 table->AVFSGB_FUSE_TABLE[1].m1 =
1606 table->AVFSGB_FUSE_TABLE[1].m2 =
1608 table->AVFSGB_FUSE_TABLE[1].b =
1610 table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;
1611 table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;
1612 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1668 struct SMU75_Discrete_DpmTable *table)
1676 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1681 table->VRConfig |= config;
1690 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1693 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1696 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1702 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1712 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1716 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1724 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1925 struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1938 vegam_populate_smc_voltage_tables(hwmgr, table);
1940 table->SystemFlags = 0;
1943 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1947 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1950 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1953 result = vegam_populate_ulv_state(hwmgr, table);
1960 result = vegam_populate_smc_link_level(hwmgr, table);
1972 result = vegam_populate_smc_acpi_level(hwmgr, table);
1976 result = vegam_populate_smc_vce_level(hwmgr, table);
1988 result = vegam_populate_smc_uvd_level(hwmgr, table);
1992 result = vegam_populate_smc_boot_level(hwmgr, table);
2016 table->CurrSclkPllRange = 0xff;
2017 table->GraphicsVoltageChangeEnable = 1;
2018 table->GraphicsThermThrottleEnable = 1;
2019 table->GraphicsInterval = 1;
2020 table->VoltageInterval = 1;
2021 table->ThermalInterval = 1;
2022 table->TemperatureLimitHigh =
2025 table->TemperatureLimitLow =
2028 table->MemoryVoltageChangeEnable = 1;
2029 table->MemoryInterval = 1;
2030 table->VoltageResponseTime = 0;
2031 table->PhaseResponseTime = 0;
2032 table->MemoryThermThrottleEnable = 1;
2037 table->PCIeBootLinkLevel =
2039 table->PCIeGenInterval = 1;
2040 table->VRConfig = 0;
2042 result = vegam_populate_vr_config(hwmgr, table);
2046 table->ThermGpio = 17;
2047 table->SclkStepSize = 0x4000;
2051 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2053 table->VRHotLevel =
2056 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2063 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2070 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2078 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2085 table->ThermOutPolarity =
2088 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2095 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2097 table->ThermOutGpio = 17;
2098 table->ThermOutPolarity = 1;
2099 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2102 /* Populate BIF_SCLK levels into SMC DPM table */
2111 table->Ulv.BifSclkDfs =
2114 table->LinkLevel[i - 1].BifSclkDfs =
2119 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2121 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2122 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2123 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2124 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2125 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2126 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2127 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2128 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2129 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2130 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2136 (uint8_t *)&(table->SystemFlags),