powerplay/hwmgr/smu8_hwmgr.c

790 	struct smu8_hwmgr *hw_data = hwmgr->backend;
792 	if (hw_data->is_nb_dpm_enabled) {
861 	struct smu8_hwmgr *hw_data = hwmgr->backend;
865 	if (hw_data->sys_info.nb_dpm_enable) {
866 		disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
867 		enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
923 	struct smu8_hwmgr *hw_data = hwmgr->backend;
925 	hw_data->disp_clk_bypass_pending = false;
926 	hw_data->disp_clk_bypass = false;
931 	struct smu8_hwmgr *hw_data = hwmgr->backend;
933 	hw_data->is_nb_dpm_enabled = false;
938 	struct smu8_hwmgr *hw_data = hwmgr->backend;
940 	hw_data->cc6_settings.cc6_setting_changed = false;
941 	hw_data->cc6_settings.cpu_pstate_separation_time = 0;
942 	hw_data->cc6_settings.cpu_cc6_disable = false;
943 	hw_data->cc6_settings.cpu_pstate_disable = false;
1455 	struct smu8_hwmgr *hw_data = hwmgr->backend;
1458 	if (hw_data->cc6_settings.cc6_setting_changed) {
1460 		hw_data->cc6_settings.cc6_setting_changed = false;
1462 		smu8_hw_print_display_cfg(&hw_data->cc6_settings);
1464 		data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1468 		data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1471 		data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1490 	struct smu8_hwmgr *hw_data = hwmgr->backend;
1493 	    hw_data->cc6_settings.cpu_pstate_separation_time ||
1494 	    cc6_disable != hw_data->cc6_settings.cpu_cc6_disable ||
1495 	    pstate_disable != hw_data->cc6_settings.cpu_pstate_disable ||
1496 	    pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) {
1498 		hw_data->cc6_settings.cc6_setting_changed = true;
1500 		hw_data->cc6_settings.cpu_pstate_separation_time =
1502 		hw_data->cc6_settings.cpu_cc6_disable =
1504 		hw_data->cc6_settings.cpu_pstate_disable =
1506 		hw_data->cc6_settings.nb_pstate_switch_disable =