pm/legacy-dpm/amdgpu_si_dpm.c

2402 	if (state->performance_level_count == 0)
2405 	if (smc_state->levelCount != state->performance_level_count)
2416 	for (i = 1; i < state->performance_level_count; i++) {
2483 	if (state->performance_level_count == 0)
2486 	if (smc_state->levelCount != state->performance_level_count)
2507 	for (i = 0; i < state->performance_level_count; i++) {
3178 	if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3179 	    current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3196 	if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3197 	    current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3484 	for (i = ps->performance_level_count - 2; i >= 0; i--) {
3489 		for (i = 0; i < ps->performance_level_count; i++) {
3509 	for (i = 0; i < ps->performance_level_count; i++) {
3535 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3536 		vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3543 		sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3544 		vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3565 		for (i = 1; i < ps->performance_level_count; i++) {
3569 		for (i = 0; i < ps->performance_level_count; i++) {
3574 		for (i = 1; i < ps->performance_level_count; i++) {
3584 		for (i = 1; i < ps->performance_level_count; i++) {
3588 		for (i = 0; i < ps->performance_level_count; i++) {
3593 		for (i = 1; i < ps->performance_level_count; i++) {
3601 	for (i = 0; i < ps->performance_level_count; i++)
3605 	for (i = 0; i < ps->performance_level_count; i++) {
3622 	for (i = 0; i < ps->performance_level_count; i++) {
3630 	for (i = 0; i < ps->performance_level_count; i++) {
3860 	u32 levels = ps->performance_level_count;
4786 	for (i = 0; i < state->performance_level_count; i++) {
5453 	for (i = 0; i < ps->performance_level_count - 1; i++)
5456 	smc_state->levels[ps->performance_level_count - 1].bSP =
5580 	if (state->performance_level_count >= 9)
5583 	if (state->performance_level_count < 2) {
5591 	for (i = 0; i <= state->performance_level_count - 2; i++) {
5609 		high_bsp = (i == state->performance_level_count - 2) ?
5684 	if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5687 	threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5701 	for (i = 0; i < state->performance_level_count; i++) {
5762 					new_state->performance_level_count);
6117 	for (i = 0; i < state->performance_level_count; i++) {
6178 					   sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6197 	for (i = 0; i < state->performance_level_count; i++) {
7191 	ps->performance_level_count = index + 1;
7538 	if (current_index >= ps->performance_level_count) {
7902 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7914 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7929 	for (i = 0; i < ps->performance_level_count; i++) {
7986 	if (si_cps->performance_level_count != si_rps->performance_level_count) {
7991 	for (i = 0; i < si_cps->performance_level_count; i++) {
8024 		if (pl_index < ps->performance_level_count) {
8032 		if (pl_index < ps->performance_level_count) {