Lines Matching defs:pp_handle
37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
39 #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev))
50 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle,
66 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle,
98 (adev)->powerplay.pp_handle, block_type, gate));
114 struct smu_context *smu = adev->powerplay.pp_handle;
129 void *pp_handle = adev->powerplay.pp_handle;
138 ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
148 void *pp_handle = adev->powerplay.pp_handle;
157 ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
174 adev->powerplay.pp_handle,
186 void *pp_handle = adev->powerplay.pp_handle;
206 ret = pp_funcs->get_asic_baco_capability(pp_handle,
217 void *pp_handle = adev->powerplay.pp_handle;
225 ret = pp_funcs->asic_reset_mode_2(pp_handle);
235 void *pp_handle = adev->powerplay.pp_handle;
243 ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle);
253 void *pp_handle = adev->powerplay.pp_handle;
262 ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
267 ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
276 struct smu_context *smu = adev->powerplay.pp_handle;
290 struct smu_context *smu = adev->powerplay.pp_handle;
315 adev->powerplay.pp_handle, type, en);
330 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
343 void *pp_handle = adev->powerplay.pp_handle;
347 ret = pp_funcs->set_df_cstate(pp_handle, cstate);
356 struct smu_context *smu = adev->powerplay.pp_handle;
370 void *pp_handle = adev->powerplay.pp_handle;
377 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle);
387 void *pp_handle = adev->powerplay.pp_handle;
394 ret = pp_funcs->set_clockgating_by_smu(pp_handle,
405 void *pp_handle = adev->powerplay.pp_handle;
412 ret = pp_funcs->smu_i2c_bus_access(pp_handle,
434 smu_set_ac_dc(adev->powerplay.pp_handle);
451 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle,
468 ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit);
482 ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit);
510 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);
582 r = pp_funcs->load_firmware(adev->powerplay.pp_handle);
602 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle,
612 struct smu_context *smu = adev->powerplay.pp_handle;
627 struct smu_context *smu = adev->powerplay.pp_handle;
654 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle,
668 struct smu_context *smu = adev->powerplay.pp_handle;
689 struct smu_context *smu = adev->powerplay.pp_handle;
706 struct smu_context *smu = adev->powerplay.pp_handle;
721 struct smu_context *smu = adev->powerplay.pp_handle;
736 struct smu_context *smu = adev->powerplay.pp_handle;
751 struct smu_context *smu = adev->powerplay.pp_handle;
766 struct smu_context *smu = adev->powerplay.pp_handle;
781 struct smu_context *smu = adev->powerplay.pp_handle;
801 (adev)->powerplay.pp_handle, state));
808 struct smu_context *smu = adev->powerplay.pp_handle;
831 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle,
850 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle);
885 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);
950 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle,
973 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle,
991 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle,
1008 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle,
1027 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle,
1048 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle,
1068 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle,
1088 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle,
1107 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle,
1123 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle,
1141 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle,
1158 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle);
1173 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value);
1195 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle);
1210 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value);
1233 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle,
1250 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle,
1267 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle,
1284 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle,
1301 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle,
1318 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle,
1335 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle,
1352 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle,
1369 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle,
1388 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
1407 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle,
1437 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle,
1455 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle,
1466 struct smu_context *smu = adev->powerplay.pp_handle;
1474 * as its pp_handle is casted directly from adev.
1479 hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;
1496 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle,
1506 struct smu_context *smu = adev->powerplay.pp_handle;
1532 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle,
1550 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle,
1568 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle,
1586 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle,
1605 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle,
1623 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle,
1640 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle,
1657 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle,
1672 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle);
1686 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle,
1703 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle,
1719 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle,
1733 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle,
1748 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle,
1765 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle,
1783 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle,
1801 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle,