Cross Reference: dcn_3_1_5_offset.h
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dcn_3_1_5_offset.h
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
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defs:regDCCG_VSYNC_OTG5_LATCH_VALUE
188
#define
regDCCG_VSYNC_OTG5_LATCH_VALUE
0x00b5