Lines Matching refs:DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM4_LS_READY_INT_XIRQ_IRQ_SEL_MASK
2744 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM4_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00200000L