Lines Matching refs:x19
146 #define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
174 #define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
260 #define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS__SHIFT 0x19
1332 #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
1364 #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
1396 #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
2012 #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
2588 #define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
2786 #define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
2972 #define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
3030 #define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
3078 #define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
3172 #define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
3240 #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
3394 #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
3492 #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
3532 #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
3786 #define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x19
3882 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
4180 #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
4810 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
4904 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
4968 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
5032 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
5092 #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
5124 #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
5168 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
5780 #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
5820 #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
6074 #define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x19
6170 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
6468 #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
7098 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
7192 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
7256 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
7320 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
7380 #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
7412 #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
7456 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
8174 #define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x19
8350 #define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19
9136 #define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x19
9312 #define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19
10214 #define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19