inc/hw/clk_mgr.h

49 	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
50 	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
51 	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
52 	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
53 	uint32_t CLK1_CLK3_DS_CNTL;	//dcf_deep_sleep_divider
54 	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
56 	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
57 	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
58 	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
59 	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
65 	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
66 	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
67 	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
68 	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
69 	uint32_t CLK1_CLK3_DS_CNTL;	//dcf_deep_sleep_divider
70 	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
72 	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
73 	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
74 	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
75 	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
153 	uint32_t dcfclk;
154 	uint32_t dcf_deep_sleep_divider;
155 	uint32_t dcf_deep_sleep_allow;
156 	uint32_t dprefclk;
157 	uint32_t dispclk;
158 	uint32_t dppclk;
159 	uint32_t dtbclk;
161 	uint32_t dppclk_bypass;
162 	uint32_t dcfclk_bypass;
163 	uint32_t dprefclk_bypass;
164 	uint32_t dispclk_bypass;
168 	uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
169 	uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
170 	uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
171 	uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
172 	uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
174 	uint32_t CLK0_CLK8_BYPASS_CNTL;  //dcfclk bypass
175 	uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
176 	uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
180 	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
181 	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
182 	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
183 	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
184 	uint32_t CLK1_CLK3_DS_CNTL;		//dcf_deep_sleep_divider
185 	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
187 	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
188 	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
189 	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
190 	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
196 		uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
197 		uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
198 		uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
199 		uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
200 		uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
205 	uint32_t dcfclk_bypass;
206 	uint32_t dispclk_pypass;
207 	uint32_t dprefclk_bypass;
242 	uint32_t dprefclk_khz;