dml/dcn321/dcn321_fpu.c

344 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
365 		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)
366 			max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
367 		if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz)
368 			max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
369 		if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz)
370 			max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
371 		if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz)
372 			max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
373 		if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz)
374 			max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
375 		if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz)
376 			max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
377 		if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz)
378 			max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
380 		if (bw_params->clk_table.entries[i].memclk_mhz > 0) {
382 			if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz)
385 		if (bw_params->clk_table.entries[i].fclk_mhz > 0) {
387 			if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz)
390 		if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) {
392 			if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz)
399 		override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data);
403 		bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms;
404 		bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms;
407 	if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
408 		min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
457 		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
468 			entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
524 			if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
525 				table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
535 				if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
536 					table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
610 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
708 			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
709 				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
710 			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
711 				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
712 			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
713 				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
714 			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
715 				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
742 		num_uclk_states = bw_params->clk_table.num_entries;
746 			dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
748 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
749 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
758 							bw_params->clk_table.entries[j].memclk_mhz * 16;
774 					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
789 			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
804 			/* Populate from bw_params for DTBCLK, SOCCLK */
806 				if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
809 					dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
811 			} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
812 				dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
815 			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
818 				dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
825 			/* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
831 		build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,