dml/dcn314/display_mode_vba_314.c

1079 	prefetch_bw_pr = dml_min(1, myPipe->VRatio) * prefetch_bw_pr;
1592 	max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
1593 	max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
1971 		*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
1979 		*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
2035 	double IdealFabricAndSDPPortBandwidthPerState = dml_min(
2041 		v->ReturnBW = dml_min(
2045 		v->ReturnBW = dml_min(
2074 			v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
2078 			v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
2083 						v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
2096 				v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
2100 				v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
2104 							v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
2490 	VMDataOnlyReturnBW = dml_min(
2491 			dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
2664 					dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
2717 			v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
3662 			min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
3664 			min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
3678 			min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
3841 		dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
4055 			v->PSCL_FACTOR[k] = dml_min(
4059 			v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
4065 							v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
4073 				v->PSCL_FACTOR_CHROMA[k] = dml_min(
4077 				v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
4081 							v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
4083 							v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
4119 		v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
4120 		v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
4396 							dml_min(600.0, v->PHYCLKPerState[i]) * 10,
5135 			double IdealFabricAndSDPPortBandwidthPerState = dml_min(
5139 			double PixelDataOnlyReturnBWPerState = dml_min(
5142 			double PixelMixedWithVMDataReturnBWPerState = dml_min(
5175 			v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
5176 					dml_min(
5229 			VMDataOnlyReturnBWPerState = dml_min(
5230 					dml_min(
5737 		v->LBLatencyHidingSourceLinesY = dml_min(
5741 		v->LBLatencyHidingSourceLinesC = dml_min(
5782 			v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
5794 			v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
6503 			TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
6515 						+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
6545 		EffectiveCompressedBufferSize = dml_min(
6548 					+ dml_min((ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate,
6558 		EffectiveCompressedBufferSize = dml_min(
6615 	PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth, EffectiveCompressedBufferSize);
6957 			SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
6959 			SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
6993 			swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
6997 				swath_width_chroma_ub[k] = dml_min(
7006 			swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
7010 				swath_width_chroma_ub[k] = dml_min(
7282 			v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
7345 	unsigned int vblank_nom_input = VBlankNom; //dml_min(VBlankNom, vblank_nom_default_in_line);
7348 	vblank_size = (unsigned int) dml_min(vblank_actual, vblank_avail);