dml/dcn31/dcn31_fpu.c

458 	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
459 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
460 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
461 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
469 	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
474 			context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
476 				dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
478 				dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
582 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
585 	struct clk_limit_table *clk_table = &bw_params->clk_table;
597 	dcn3_1_soc.num_chans = bw_params->num_channels;
660 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
662 	struct clk_limit_table *clk_table = &bw_params->clk_table;
670 	if (bw_params->num_channels > 0)
671 		dcn3_15_soc.num_chans = bw_params->num_channels;
672 	if (bw_params->dram_channel_width_bytes > 0)
673 		dcn3_15_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;
721 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
724 	struct clk_limit_table *clk_table = &bw_params->clk_table;
736 	dcn3_16_soc.num_chans = bw_params->num_channels;