Lines Matching defs:disp_ttu_regs
897 display_ttu_regs_st *disp_ttu_regs,
1030 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
1707 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l
1709 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l
1711 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c
1713 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c
1715 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
1717 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0
1719 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
1721 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1
1723 disp_ttu_regs->qos_level_low_wm = 0;
1724 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1725 disp_ttu_regs->qos_level_high_wm = (unsigned int)(4.0 * (double)htotal
1727 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
1729 disp_ttu_regs->qos_level_flip = 14;
1730 disp_ttu_regs->qos_level_fixed_l = 8;
1731 disp_ttu_regs->qos_level_fixed_c = 8;
1732 disp_ttu_regs->qos_level_fixed_cur0 = 8;
1733 disp_ttu_regs->qos_ramp_disable_l = 0;
1734 disp_ttu_regs->qos_ramp_disable_c = 0;
1735 disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1737 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1738 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1740 print__ttu_regs_st(mode_lib, disp_ttu_regs);