Lines Matching defs:disp_ttu_regs
51 display_ttu_regs_st *disp_ttu_regs,
789 display_ttu_regs_st *disp_ttu_regs,
917 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
1513 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
1515 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
1517 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
1519 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
1521 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
1523 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
1525 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
1527 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
1529 disp_ttu_regs->qos_level_low_wm = 0;
1530 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1531 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1533 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
1535 disp_ttu_regs->qos_level_flip = 14;
1536 disp_ttu_regs->qos_level_fixed_l = 8;
1537 disp_ttu_regs->qos_level_fixed_c = 8;
1538 disp_ttu_regs->qos_level_fixed_cur0 = 8;
1539 disp_ttu_regs->qos_ramp_disable_l = 0;
1540 disp_ttu_regs->qos_ramp_disable_c = 0;
1541 disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1543 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1544 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1546 print__ttu_regs_st(mode_lib, disp_ttu_regs);