Lines Matching defs:hws
61 hws->ctx
63 hws->regs->reg
70 hws->shifts->field_name, hws->masks->field_name
238 struct dce_hwseq *hws,
246 if (hws->ctx->dc->debug.disable_dsc_power_gate)
249 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
250 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
252 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
253 hws->ctx->dc->res_pool->dccg, dsc_inst);
300 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
301 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
302 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
303 hws->ctx->dc->res_pool->dccg, dsc_inst);
308 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
313 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
327 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
393 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
412 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
422 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
424 if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)
427 if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)
428 hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(
429 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);