dc/dcn20/dcn20_resource.c

736 	uint32_t inst)
744 	if (dpp2_construct(dpp, ctx, inst,
745 			&tf_regs[inst], &tf_shift, &tf_mask))
754 	struct dc_context *ctx, uint32_t inst)
764 	dcn20_ipp_construct(ipp, ctx, inst,
765 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
771 	struct dc_context *ctx, uint32_t inst)
781 	dcn20_opp_construct(opp, ctx, inst,
782 			&opp_regs[inst], &opp_shift, &opp_mask);
788 	uint32_t inst)
796 	dce110_aux_engine_construct(aux_engine, ctx, inst,
798 				    &aux_engine_regs[inst],
826 	uint32_t inst)
834 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
835 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
893 	tgn10->base.inst = instance;
953 			&panel_cntl_regs[init_data->inst],
993 		struct dc_context *ctx, unsigned int inst)
995 	return dce_audio_create(ctx, inst,
996 			&audio_regs[inst], &audio_shift, &audio_mask);
1064 	struct dc_context *ctx, uint32_t inst)
1074 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1201 	uint32_t inst)
1209 	if (hubp2_construct(hubp2, ctx, inst,
1210 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1240 	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1329 	if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1331 		res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1479 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1564 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1934 		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
1938 		if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
2172 	sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;