Lines Matching refs:type
227 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
228 type DIG_ENABLE;\
229 type DIG_HPD_SELECT;\
230 type DIG_MODE;\
231 type DIG_FE_SOURCE_SELECT;\
232 type DIG_CLOCK_PATTERN;\
233 type DPHY_BYPASS;\
234 type DPHY_ATEST_SEL_LANE0;\
235 type DPHY_ATEST_SEL_LANE1;\
236 type DPHY_ATEST_SEL_LANE2;\
237 type DPHY_ATEST_SEL_LANE3;\
238 type DPHY_PRBS_EN;\
239 type DPHY_PRBS_SEL;\
240 type DPHY_SYM1;\
241 type DPHY_SYM2;\
242 type DPHY_SYM3;\
243 type DPHY_SYM4;\
244 type DPHY_SYM5;\
245 type DPHY_SYM6;\
246 type DPHY_SYM7;\
247 type DPHY_SYM8;\
248 type DPHY_SCRAMBLER_BS_COUNT;\
249 type DPHY_SCRAMBLER_ADVANCE;\
250 type DPHY_RX_FAST_TRAINING_CAPABLE;\
251 type DPHY_LOAD_BS_COUNT;\
252 type DPHY_TRAINING_PATTERN_SEL;\
253 type DP_DPHY_HBR2_PATTERN_CONTROL;\
254 type DP_LINK_TRAINING_COMPLETE;\
255 type DP_IDLE_BS_INTERVAL;\
256 type DP_VBID_DISABLE;\
257 type DP_VID_ENHANCED_FRAME_MODE;\
258 type DP_VID_STREAM_ENABLE;\
259 type DP_UDI_LANES;\
260 type DP_SEC_GSP0_LINE_NUM;\
261 type DP_SEC_GSP0_PRIORITY;\
262 type DP_MSE_SAT_SRC0;\
263 type DP_MSE_SAT_SRC1;\
264 type DP_MSE_SAT_SRC2;\
265 type DP_MSE_SAT_SRC3;\
266 type DP_MSE_SAT_SLOT_COUNT0;\
267 type DP_MSE_SAT_SLOT_COUNT1;\
268 type DP_MSE_SAT_SLOT_COUNT2;\
269 type DP_MSE_SAT_SLOT_COUNT3;\
270 type DP_MSE_SAT_UPDATE;\
271 type DP_MSE_16_MTP_KEEPOUT;\
272 type DC_HPD_EN;\
273 type TMDS_CTL0;\
274 type AUX_HPD_SEL;\
275 type AUX_LS_READ_EN;\
276 type AUX_RX_RECEIVE_WINDOW
279 #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
280 type RDPCS_PHY_DP_TX0_DATA_EN;\
281 type RDPCS_PHY_DP_TX1_DATA_EN;\
282 type RDPCS_PHY_DP_TX2_DATA_EN;\
283 type RDPCS_PHY_DP_TX3_DATA_EN;\
284 type RDPCS_PHY_DP_TX0_PSTATE;\
285 type RDPCS_PHY_DP_TX1_PSTATE;\
286 type RDPCS_PHY_DP_TX2_PSTATE;\
287 type RDPCS_PHY_DP_TX3_PSTATE;\
288 type RDPCS_PHY_DP_TX0_MPLL_EN;\
289 type RDPCS_PHY_DP_TX1_MPLL_EN;\
290 type RDPCS_PHY_DP_TX2_MPLL_EN;\
291 type RDPCS_PHY_DP_TX3_MPLL_EN;\
292 type RDPCS_TX_FIFO_LANE0_EN;\
293 type RDPCS_TX_FIFO_LANE1_EN;\
294 type RDPCS_TX_FIFO_LANE2_EN;\
295 type RDPCS_TX_FIFO_LANE3_EN;\
296 type RDPCS_EXT_REFCLK_EN;\
297 type RDPCS_TX_FIFO_EN;\
298 type UNIPHY_LINK_ENABLE;\
299 type UNIPHY_CHANNEL0_XBAR_SOURCE;\
300 type UNIPHY_CHANNEL1_XBAR_SOURCE;\
301 type UNIPHY_CHANNEL2_XBAR_SOURCE;\
302 type UNIPHY_CHANNEL3_XBAR_SOURCE;\
303 type UNIPHY_CHANNEL0_INVERT;\
304 type UNIPHY_CHANNEL1_INVERT;\
305 type UNIPHY_CHANNEL2_INVERT;\
306 type UNIPHY_CHANNEL3_INVERT;\
307 type UNIPHY_LINK_ENABLE_HPD_MASK;\
308 type UNIPHY_LANE_STAGGER_DELAY;\
309 type RDPCS_SRAMCLK_BYPASS;\
310 type RDPCS_SRAMCLK_EN;\
311 type RDPCS_SRAMCLK_CLOCK_ON;\
312 type DPCS_TX_FIFO_EN;\
313 type RDPCS_PHY_DP_TX0_DISABLE;\
314 type RDPCS_PHY_DP_TX1_DISABLE;\
315 type RDPCS_PHY_DP_TX2_DISABLE;\
316 type RDPCS_PHY_DP_TX3_DISABLE;\
317 type RDPCS_PHY_DP_TX0_CLK_RDY;\
318 type RDPCS_PHY_DP_TX1_CLK_RDY;\
319 type RDPCS_PHY_DP_TX2_CLK_RDY;\
320 type RDPCS_PHY_DP_TX3_CLK_RDY;\
321 type RDPCS_PHY_DP_TX0_REQ;\
322 type RDPCS_PHY_DP_TX1_REQ;\
323 type RDPCS_PHY_DP_TX2_REQ;\
324 type RDPCS_PHY_DP_TX3_REQ;\
325 type RDPCS_PHY_DP_TX0_ACK;\
326 type RDPCS_PHY_DP_TX1_ACK;\
327 type RDPCS_PHY_DP_TX2_ACK;\
328 type RDPCS_PHY_DP_TX3_ACK;\
329 type RDPCS_PHY_DP_TX0_RESET;\
330 type RDPCS_PHY_DP_TX1_RESET;\
331 type RDPCS_PHY_DP_TX2_RESET;\
332 type RDPCS_PHY_DP_TX3_RESET;\
333 type RDPCS_PHY_RESET;\
334 type RDPCS_PHY_CR_MUX_SEL;\
335 type RDPCS_PHY_REF_RANGE;\
336 type RDPCS_PHY_DP4_POR;\
337 type RDPCS_SRAM_BYPASS;\
338 type RDPCS_SRAM_EXT_LD_DONE;\
339 type RDPCS_PHY_DP_TX0_TERM_CTRL;\
340 type RDPCS_PHY_DP_TX1_TERM_CTRL;\
341 type RDPCS_PHY_DP_TX2_TERM_CTRL;\
342 type RDPCS_PHY_DP_TX3_TERM_CTRL;\
343 type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
344 type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
345 type RDPCS_PHY_DP_MPLLB_SSC_EN;\
346 type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
347 type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
348 type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
349 type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
350 type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
351 type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
352 type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
353 type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
354 type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
355 type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
356 type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
357 type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
358 type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
359 type RDPCS_PHY_TX_VBOOST_LVL;\
360 type RDPCS_PHY_HDMIMODE_ENABLE;\
361 type RDPCS_PHY_DP_REF_CLK_EN;\
362 type RDPCS_PLL_UPDATE_DATA;\
363 type RDPCS_SRAM_INIT_DONE;\
364 type RDPCS_TX_CR_ADDR;\
365 type RDPCS_TX_CR_DATA;\
366 type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
367 type RDPCS_PHY_DP_MPLLB_STATE;\
368 type RDPCS_PHY_DP_TX0_WIDTH;\
369 type RDPCS_PHY_DP_TX0_RATE;\
370 type RDPCS_PHY_DP_TX1_WIDTH;\
371 type RDPCS_PHY_DP_TX1_RATE;\
372 type RDPCS_PHY_DP_TX2_WIDTH;\
373 type RDPCS_PHY_DP_TX2_RATE;\
374 type RDPCS_PHY_DP_TX3_WIDTH;\
375 type RDPCS_PHY_DP_TX3_RATE;\
376 type DPCS_SYMCLK_CLOCK_ON;\
377 type DPCS_SYMCLK_GATE_DIS;\
378 type DPCS_SYMCLK_EN;\
379 type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
380 type RDPCS_SYMCLK_DIV2_GATE_DIS;\
381 type RDPCS_SYMCLK_DIV2_EN;\
382 type DPCS_TX_DATA_SWAP;\
383 type DPCS_TX_DATA_ORDER_INVERT;\
384 type DPCS_TX_FIFO_RD_START_DELAY;\
385 type RDPCS_TX_FIFO_RD_START_DELAY;\
386 type RDPCS_REG_FIFO_ERROR_MASK;\
387 type RDPCS_TX_FIFO_ERROR_MASK;\
388 type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
389 type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
390 type RDPCS_PHY_DPALT_DP4;\
391 type RDPCS_PHY_DPALT_DISABLE;\
392 type RDPCS_PHY_DPALT_DISABLE_ACK;\
393 type RDPCS_PHY_DP_MPLLB_V2I;\
394 type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
395 type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
396 type RDPCS_PHY_RX_VREF_CTRL;\
397 type RDPCS_PHY_DP_MPLLB_CP_INT;\
398 type RDPCS_PHY_DP_MPLLB_CP_PROP;\
399 type RDPCS_PHY_RX_REF_LD_VAL;\
400 type RDPCS_PHY_RX_VCO_LD_VAL;\
401 type DPCSTX_DEBUG_CONFIG; \
402 type RDPCSTX_DEBUG_CONFIG; \
403 type RDPCS_PHY_DP_TX0_EQ_MAIN;\
404 type RDPCS_PHY_DP_TX0_EQ_PRE;\
405 type RDPCS_PHY_DP_TX0_EQ_POST;\
406 type RDPCS_PHY_DP_TX1_EQ_MAIN;\
407 type RDPCS_PHY_DP_TX1_EQ_PRE;\
408 type RDPCS_PHY_DP_TX1_EQ_POST;\
409 type RDPCS_PHY_DP_TX2_EQ_MAIN;\
410 type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
411 type RDPCS_PHY_DP_TX2_EQ_PRE;\
412 type RDPCS_PHY_DP_TX2_EQ_POST;\
413 type RDPCS_PHY_DP_TX3_EQ_MAIN;\
414 type RDPCS_PHY_DCO_RANGE;\
415 type RDPCS_PHY_DCO_FINETUNE;\
416 type RDPCS_PHY_DP_TX3_EQ_PRE;\
417 type RDPCS_PHY_DP_TX3_EQ_POST;\
418 type RDPCS_PHY_SUP_PRE_HP;\
419 type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
420 type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
421 type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
422 type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
423 type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
424 type UNIPHYA_SOFT_RESET;\
425 type UNIPHYB_SOFT_RESET;\
426 type UNIPHYC_SOFT_RESET;\
427 type UNIPHYD_SOFT_RESET;\
428 type UNIPHYE_SOFT_RESET;\
429 type UNIPHYF_SOFT_RESET
431 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
432 type DIG_LANE0EN;\
433 type DIG_LANE1EN;\
434 type DIG_LANE2EN;\
435 type DIG_LANE3EN;\
436 type DIG_CLK_EN;\
437 type SYMCLKA_CLOCK_ENABLE;\
438 type DPHY_FEC_EN;\
439 type DPHY_FEC_READY_SHADOW;\
440 type DPHY_FEC_ACTIVE_STATUS;\
441 DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
442 type VCO_LD_VAL_OVRD;\
443 type VCO_LD_VAL_OVRD_EN;\
444 type REF_LD_VAL_OVRD;\
445 type REF_LD_VAL_OVRD_EN;\
446 type AUX_RX_START_WINDOW; \
447 type AUX_RX_HALF_SYM_DETECT_LEN; \
448 type AUX_RX_TRANSITION_FILTER_EN; \
449 type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
450 type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
451 type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
452 type AUX_RX_PHASE_DETECT_LEN; \
453 type AUX_RX_DETECTION_THRESHOLD; \
454 type AUX_TX_PRECHARGE_LEN; \
455 type AUX_TX_PRECHARGE_SYMBOLS; \
456 type AUX_MODE_DET_CHECK_DELAY;\
457 type DPCS_DBG_CBUS_DIS;\
458 type AUX_RX_PRECHARGE_SKIP;\
459 type AUX_RX_TIMEOUT_LEN;\
460 type AUX_RX_TIMEOUT_LEN_MUL
462 #define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \
463 type TMDS_SYNC_DCBAL_EN;\
464 type PHY_HPO_DIG_SRC_SEL;\
465 type PHY_HPO_ENC_SRC_SEL;\
466 type DPCS_TX_HDMI_FRL_MODE;\
467 type DPCS_TX_DATA_SWAP_10_BIT;\
468 type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
469 type RDPCS_TX_CLK_EN
471 #define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
472 type ENC_TYPE_SEL;\
473 type HPO_DP_ENC_SEL;\
474 type HPO_HDMI_ENC_SEL
476 #define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
477 type DIG_FIFO_OUTPUT_PIXEL_MODE