dc/dce/dce_clk_mgr.c

497 	struct dm_pp_display_configuration *pp_display_cfg)
507 			&pp_display_cfg->disp_configs[num_cfgs];
545 	pp_display_cfg->display_count = num_cfgs;
602 	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
604 	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
606 	dce110_fill_display_configs(context, pp_display_cfg);
608 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
609 		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
616 	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
618 	pp_display_cfg->all_displays_in_sync =
620 	pp_display_cfg->nb_pstate_switch_disable =
622 	pp_display_cfg->cpu_cc6_disable =
624 	pp_display_cfg->cpu_pstate_disable =
626 	pp_display_cfg->cpu_pstate_separation_time =
629 	pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
632 	pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
643 	pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?
644 			pp_display_cfg->min_engine_clock_khz : 0;
646 	pp_display_cfg->min_engine_clock_deep_sleep_khz
649 	pp_display_cfg->avail_mclk_switch_time_us =
652 	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
654 	pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
656 	dce110_fill_display_configs(context, pp_display_cfg);
659 	if (pp_display_cfg->display_count == 1) {
663 		pp_display_cfg->crtc_index =
664 			pp_display_cfg->disp_configs[0].pipe_idx;
665 		pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
668 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
669 		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);