Lines Matching refs:clock_table
455 const DpmClocks_316_t *clock_table,
464 if (clock_table->SocVoltage[i] == voltage) {
466 } else if (clock_table->SocVoltage[i] >= max_voltage &&
467 clock_table->SocVoltage[i] < voltage) {
468 max_voltage = clock_table->SocVoltage[i];
480 const DpmClocks_316_t *clock_table)
493 if (clock_table->DfPstateTable[i].FClk != 0) {
508 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
509 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
510 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
511 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
519 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
520 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
521 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
522 switch (clock_table->DfPstateTable[j].WckRatio) {
532 temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
535 temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);