clk_mgr/dcn315/dcn315_clk_mgr.c

482 		const DpmClocks_315_t *clock_table)
486 	uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1;
490 	for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
494 		for (j = clock_table->NumDfPstatesEnabled - 2; j >= 0; j--) {
495 			if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i])
499 		if (i == clock_table->NumDcfClkLevelsEnabled - 1)
504 			if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
511 		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[max_pstate].FClk;
512 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
513 		bw_params->clk_table.entries[i].voltage = clock_table->SocVoltage[i];
514 		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
515 		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
516 		bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
517 		bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i];
523 		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[0].FClk;
524 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk;
525 		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[0].Voltage;
526 		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0];
529 	} else if (clock_table->NumDcfClkLevelsEnabled != clock_table->NumSocClkLevelsEnabled) {
530 		bw_params->clk_table.entries[i-1].voltage = clock_table->SocVoltage[clock_table->NumSocClkLevelsEnabled - 1];
531 		bw_params->clk_table.entries[i-1].socclk_mhz = clock_table->SocClocks[clock_table->NumSocClkLevelsEnabled - 1];
532 		bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
533 		bw_params->clk_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1];