clk_mgr/dcn314/dcn314_clk_mgr.c

569 						    const DpmClocks314_t *clock_table)
577 	for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) {
578 		if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) &&
579 		    clock_table->DfPstateTable[i].FClk > max_fclk) {
580 			max_fclk = clock_table->DfPstateTable[i].FClk;
589 	if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
590 	    clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
591 		max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
592 		max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
599 	for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
600 		uint32_t min_fclk = clock_table->DfPstateTable[0].FClk;
603 		for (j = 1; j < clock_table->NumDfPstatesEnabled; j++) {
604 			if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) &&
605 			    clock_table->DfPstateTable[j].FClk < min_fclk &&
606 			    clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]) {
607 				min_fclk = clock_table->DfPstateTable[j].FClk;
614 			if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
623 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk;
624 		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage;
625 		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
626 		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
630 			clock_table->DfPstateTable[min_pstate].WckRatio);
639 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
640 		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage;
641 		bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
642 		bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
646 			clock_table->DfPstateTable[max_pstate].WckRatio);
652 	bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
653 	bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
654 	bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
655 	ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));