clk_mgr/dcn31/dcn31_clk_mgr.c

502 	DpmClocks_t *table = smu_dpm_clks->dpm_clks;
705 	smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
711 	if (smu_dpm_clks.dpm_clks == NULL) {
712 		smu_dpm_clks.dpm_clks = &dummy_clocks;
716 	ASSERT(smu_dpm_clks.dpm_clks);
755 				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
756 				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
757 				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
758 				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
759 				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
760 				   smu_dpm_clks.dpm_clks->MinGfxClk,
761 				   smu_dpm_clks.dpm_clks->MaxGfxClk);
762 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
763 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
765 					   smu_dpm_clks.dpm_clks->DcfClocks[i]);
767 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
768 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
769 					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);
771 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
772 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
773 					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);
776 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
777 					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
780 			DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
781 					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
782 					   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
783 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
784 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
785 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
791 					smu_dpm_clks.dpm_clks);
795 	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
797 				smu_dpm_clks.dpm_clks);