Lines Matching refs:clock_table
533 const DpmClocks_t *clock_table,
542 if (clock_table->SocVoltage[i] == voltage) {
544 } else if (clock_table->SocVoltage[i] >= max_voltage &&
545 clock_table->SocVoltage[i] < voltage) {
546 max_voltage = clock_table->SocVoltage[i];
557 const DpmClocks_t *clock_table)
570 if (clock_table->DfPstateTable[i].FClk != 0) {
585 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
586 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
587 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
588 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
594 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
595 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
596 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
597 switch (clock_table->DfPstateTable[j].WckRatio) {
607 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
608 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);