Lines Matching refs:DfPstateTable
570 if (clock_table->DfPstateTable[i].FClk != 0) {
594 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
595 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
596 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
597 switch (clock_table->DfPstateTable[j].WckRatio) {
607 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
608 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
780 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
781 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
782 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
783 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
784 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
785 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);