clk_mgr/dcn21/rn_clk_mgr.c

454 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
462 		if (!bw_params->wm_table.entries[i].valid)
465 		ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
466 		ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
477 				ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
479 			ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
518 		build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);
639 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
662 	bw_params->clk_table.num_entries = j + 1;
664 	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
665 		bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
666 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
667 		bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
668 		bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
669 		bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table,
670 									bw_params->clk_table.entries[i].voltage);
673 	bw_params->vram_type = bios_info->memory_type;
674 	bw_params->num_channels = bios_info->ma_channel_number;
677 		bw_params->wm_table.entries[i].wm_inst = i;
679 		if (i >= bw_params->clk_table.num_entries) {
680 			bw_params->wm_table.entries[i].valid = false;
684 		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
685 		bw_params->wm_table.entries[i].valid = true;
688 	if (bw_params->vram_type == LpDdr4MemType) {
693 		dcn21_clk_mgr_set_bw_params_wm_table(bw_params);
769 	clk_mgr->base.bw_params = &rn_bw_params;
776 			rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
779 				clk_mgr->base.bw_params->num_channels = 1;