Lines Matching defs:pp_display_cfg
121 struct dm_pp_display_configuration *pp_display_cfg)
131 &pp_display_cfg->disp_configs[num_cfgs];
169 pp_display_cfg->display_count = num_cfgs;
176 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
182 pp_display_cfg->all_displays_in_sync =
184 pp_display_cfg->nb_pstate_switch_disable =
186 pp_display_cfg->cpu_cc6_disable =
188 pp_display_cfg->cpu_pstate_disable =
190 pp_display_cfg->cpu_pstate_separation_time =
200 pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
209 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
220 pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?
221 pp_display_cfg->min_engine_clock_khz : 0;
223 pp_display_cfg->min_engine_clock_deep_sleep_khz
226 pp_display_cfg->avail_mclk_switch_time_us =
229 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
231 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
233 dce110_fill_display_configs(context, pp_display_cfg);
236 if (pp_display_cfg->display_count == 1) {
240 pp_display_cfg->crtc_index =
241 pp_display_cfg->disp_configs[0].pipe_idx;
242 pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
245 if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
246 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);