display/amdgpu_dm/amdgpu_dm_mst_types.c

812 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
822 		drm_connector = &params[i].aconnector->base;
824 		dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);
827 		memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
829 					params[i].sink->ctx->dc->res_pool->dscs[0],
830 					&params[i].sink->dsc_caps.dsc_dec_caps,
833 					params[i].timing,
834 					dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),
835 					&params[i].timing->dsc_cfg)) {
836 			params[i].timing->flags.DSC = 1;
838 			if (params[i].bpp_overwrite)
839 				params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
841 				params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
843 			if (params[i].num_slices_h)
844 				params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
846 			if (params[i].num_slices_v)
847 				params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
849 			params[i].timing->flags.DSC = 0;
851 		params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
855 		if (params[i].sink) {
856 			if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
857 				params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
859 					params[i].sink->edid_caps.display_name);
863 			params[i].timing->flags.DSC,
864 			params[i].timing->dsc_cfg.bits_per_pixel,
895 			    struct dsc_mst_fairness_params *params,
914 			kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
949 							    params[next_index].port->mgr,
950 							    params[next_index].port,
957 				vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
961 								    params[next_index].port->mgr,
962 								    params[next_index].port,
970 							    params[next_index].port->mgr,
971 							    params[next_index].port,
978 				vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
982 								    params[next_index].port->mgr,
983 								    params[next_index].port,
998 			   struct dsc_mst_fairness_params *params,
1014 				&& vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1015 				&& params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1016 			kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1040 		vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1042 						    params[next_index].port->mgr,
1043 						    params[next_index].port,
1053 			vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000);
1055 							    params[next_index].port->mgr,
1056 							    params[next_index].port,
1076 	struct dsc_mst_fairness_params params[MAX_PIPES];
1084 	memset(params, 0, sizeof(params));
1089 	/* Set up params */
1107 		params[count].timing = &stream->timing;
1108 		params[count].sink = stream->sink;
1109 		params[count].aconnector = aconnector;
1110 		params[count].port = aconnector->mst_output_port;
1111 		params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1112 		if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1114 		params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1115 		params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1116 		params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1117 		params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1118 		dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
1127 				&params[count].bw_range))
1128 			params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
1146 		vars[i + k].aconnector = params[i].aconnector;
1147 		vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1150 		ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1157 		set_dsc_configs_from_fairness_vars(params, vars, count, k);
1165 		if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1166 			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
1168 			vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1169 			ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1170 							    params[i].port, vars[i + k].pbn);
1174 			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1177 			ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1178 							    params[i].port, vars[i + k].pbn);
1188 	ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1192 	ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1196 	set_dsc_configs_from_fairness_vars(params, vars, count, k);
1612 	 *    1. dsc is possible between source and branch/leaf device (common dsc params is possible), AND