display/amdgpu_dm/amdgpu_dm.c

2812 	struct dm_crtc_state *dm_new_crtc_state;
2957 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2958 		if (dm_new_crtc_state->stream) {
2959 			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2960 			dc_stream_release(dm_new_crtc_state->stream);
2961 			dm_new_crtc_state->stream = NULL;
2963 		dm_new_crtc_state->base.color_mgmt_changed = true;
8530 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8554 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8578 		if (dm_new_crtc_state->stream) {
8579 			amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8580 							    dm_new_crtc_state->stream);
8587 		if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8591 			if (!dm_new_crtc_state->stream) {
8651 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8653 		if (dm_new_crtc_state->stream != NULL) {
8655 					dc_stream_get_status(dm_new_crtc_state->stream);
8659 									 dm_new_crtc_state->stream);
8661 				DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8690 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8771 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8773 		if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8843 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8849 		abm_changed = dm_new_crtc_state->abm_level !=
8858 		stream_update.stream = dm_new_crtc_state->stream;
8861 					dm_new_con_state, dm_new_crtc_state->stream);
8863 			stream_update.src = dm_new_crtc_state->stream->src;
8864 			stream_update.dst = dm_new_crtc_state->stream->dst;
8868 			dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8870 			stream_update.abm_level = &dm_new_crtc_state->abm_level;
8878 		status = dc_stream_get_status(dm_new_crtc_state->stream);
8899 					    dm_new_crtc_state->stream,
8920 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8924 		update_stream_irq_parameters(dm, dm_new_crtc_state);
8935 			dc_stream_retain(dm_new_crtc_state->stream);
8936 			acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8940 		amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8965 					crtc, dm_new_crtc_state, cur_crc_src))
8978 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8980 		if (dm_new_crtc_state->stream)
9253 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9256 	struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9258 	dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9265 	dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9277 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9293 	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9342 		dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9358 		if (dm_new_crtc_state->stream &&
9362 		if (dm_new_crtc_state->stream &&
9393 			dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9394 			dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9398 		if (dm_new_crtc_state->stream &&
9408 			set_freesync_fixed_config(dm_new_crtc_state);
9418 				set_freesync_fixed_config(dm_new_crtc_state);
9438 		dm_new_crtc_state->stream = NULL;
9440 		reset_freesync_config_for_crtc(dm_new_crtc_state);
9459 			WARN_ON(dm_new_crtc_state->stream);
9465 			dm_new_crtc_state->stream = new_stream;
9475 					dm_new_crtc_state->stream) != DC_OK) {
9503 	BUG_ON(dm_new_crtc_state->stream == NULL);
9509 			&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9512 	dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9518 	if (dm_new_crtc_state->base.color_mgmt_changed ||
9520 		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9526 	get_freesync_config_for_crtc(dm_new_crtc_state,
9717 	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9802 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9804 		if (!dm_new_crtc_state->stream)
9856 				dm_new_crtc_state->stream,
9866 		dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
10070 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10271 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10272 		if (dm_new_crtc_state->mpo_requested)
10451 		struct dm_crtc_state *dm_new_crtc_state =
10466 		dm_new_crtc_state->update_type = lock_and_validation_needed ?