Lines Matching refs:glc
291 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag
297 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA
299 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA
378 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1
380 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1
382 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1
584 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1
903 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1
904 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1
905 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1
937 s_buffer_store_dword s, s_rsrc, m0 glc:1
947 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1
949 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1
951 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1
953 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1
961 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1
966 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1
982 buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
983 buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
984 buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
985 buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
989 buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
990 buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
991 buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
992 buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
1005 s_buffer_store_dwordx4 s[0:3], s_rsrc, s_mem_offset glc:1