amd/amdgpu/uvd_v6_0.c

95 	if (ring == &adev->uvd.inst->ring_enc[0])
125 	if (ring == &adev->uvd.inst->ring_enc[0])
156 	if (ring == &adev->uvd.inst->ring_enc[0])
385 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
392 			r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
404 			adev->uvd.inst->ring_enc[i].funcs = NULL;
406 		adev->uvd.inst->irq.num_types = 1;
412 	ring = &adev->uvd.inst->ring;
414 	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
425 			ring = &adev->uvd.inst->ring_enc[i];
428 					     &adev->uvd.inst->irq, 0,
451 			amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
467 	struct amdgpu_ring *ring = &adev->uvd.inst->ring;
508 			ring = &adev->uvd.inst->ring_enc[i];
607 			lower_32_bits(adev->uvd.inst->gpu_addr));
609 			upper_32_bits(adev->uvd.inst->gpu_addr));
722 	struct amdgpu_ring *ring = &adev->uvd.inst->ring;
862 		ring = &adev->uvd.inst->ring_enc[0];
869 		ring = &adev->uvd.inst->ring_enc[1];
1174 		adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
1177 		adev->uvd.inst->srbm_soft_reset = 0;
1186 	if (!adev->uvd.inst->srbm_soft_reset)
1198 	if (!adev->uvd.inst->srbm_soft_reset)
1200 	srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
1228 	if (!adev->uvd.inst->srbm_soft_reset)
1254 		amdgpu_fence_process(&adev->uvd.inst->ring);
1258 			amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
1264 			amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
1629 		adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
1632 		adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
1642 		adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1655 		adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
1657 		adev->uvd.inst->irq.num_types = 1;
1659 	adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;