amd/amdgpu/amdgpu_display.c

51  * amdgpu_display_hotplug_work_func - work handler for display hotplug event
53  * @work: work struct pointer
55  * This is the hotplug event work handler (all ASICs).
56  * The work gets scheduled from the IRQ handler if there
62  * from the IRQ handler to a work handler because hotplug handler has to use
66 void amdgpu_display_hotplug_work_func(struct work_struct *work)
68 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
69 						  hotplug_work.work);
93 	struct amdgpu_flip_work *work =
97 	schedule_work(&work->flip_work.work);
100 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
110 	if (!dma_fence_add_callback(fence, &work->cb,
121 		container_of(__work, struct delayed_work, work);
122 	struct amdgpu_flip_work *work =
124 	struct amdgpu_device *adev = work->adev;
125 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
132 	for (i = 0; i < work->shared_count; ++i)
133 		if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
140 	    (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
145 	    (int)(work->target_vblank -
147 		schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
155 	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
163 		    "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
164 		    amdgpu_crtc->crtc_id, amdgpu_crtc, work);
173 	struct amdgpu_flip_work *work =
178 	r = amdgpu_bo_reserve(work->old_abo, true);
180 		amdgpu_bo_unpin(work->old_abo);
181 		amdgpu_bo_unreserve(work->old_abo);
185 	amdgpu_bo_unref(&work->old_abo);
186 	kfree(work->shared);
187 	kfree(work);
200 	struct amdgpu_flip_work *work;
206 	work = kzalloc(sizeof(*work), GFP_KERNEL);
207 	if (work == NULL)
210 	INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
211 	INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
213 	work->event = event;
214 	work->adev = adev;
215 	work->crtc_id = amdgpu_crtc->crtc_id;
216 	work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
222 	work->old_abo = gem_to_amdgpu_bo(obj);
223 	amdgpu_bo_ref(work->old_abo);
251 				&work->shared_count,
252 				&work->shared);
262 		work->base = amdgpu_bo_gpu_offset(new_abo);
263 	work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
276 	amdgpu_crtc->pflip_works = work;
279 	DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
280 					 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
284 	amdgpu_display_flip_work_func(&work->flip_work.work);
300 	amdgpu_bo_unref(&work->old_abo);
301 	for (i = 0; i < work->shared_count; ++i)
302 		dma_fence_put(work->shared[i]);
303 	kfree(work->shared);
304 	kfree(work);